From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 19 Apr 2019 00:50:11 +0000 (-0700)
Subject: Missing close bracket
X-Git-Tag: working-ls180~1237^2~181
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=0919f36b88bed88e6dbfa23381540dc8ee035962;p=yosys.git

Missing close bracket
---

diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v
index a6f1fc9de..1d104c5d7 100644
--- a/techlibs/ice40/cells_sim.v
+++ b/techlibs/ice40/cells_sim.v
@@ -118,7 +118,7 @@ endmodule
 
 // SiliconBlue Logic Cells
 
-(* abc_box_id = 22 *
+(* abc_box_id = 22 *)
 module SB_LUT4 (output O, input I0, I1, I2, I3);
 	parameter [15:0] LUT_INIT = 0;
 	wire [7:0] s3 = I3 ? LUT_INIT[15:8] : LUT_INIT[7:0];