From: Luke Kenneth Casson Leighton Date: Thu, 6 Oct 2022 10:53:59 +0000 (+0100) Subject: add sv.cmp and try fail-first test_pysvp64dist.py X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=091c7c2f06a7c557aae12b1e84de85b12b8bde6e;p=openpower-isa.git add sv.cmp and try fail-first test_pysvp64dist.py --- diff --git a/openpower/isatables/RM-1P-2S1D.csv b/openpower/isatables/RM-1P-2S1D.csv index 7141dc95..67843900 100644 --- a/openpower/isatables/RM-1P-2S1D.csv +++ b/openpower/isatables/RM-1P-2S1D.csv @@ -7,10 +7,10 @@ crand,CROP,,1P,EXTRA3,NO,d:BT,s:BA,s:BB,0,0,0,0,0,BA_BB,BT,0 creqv,CROP,,1P,EXTRA3,NO,d:BT,s:BA,s:BB,0,0,0,0,0,BA_BB,BT,0 crorc,CROP,,1P,EXTRA3,NO,d:BT,s:BA,s:BB,0,0,0,0,0,BA_BB,BT,0 cror,CROP,,1P,EXTRA3,NO,d:BT,s:BA,s:BB,0,0,0,0,0,BA_BB,BT,0 -cmp,NORMAL,,1P,EXTRA3,NO,d:BF,s:RA,s:RB,0,RA,RB,0,0,0,BF,0 -cmpl,NORMAL,,1P,EXTRA3,NO,d:BF,s:RA,s:RB,0,RA,RB,0,0,0,BF,0 -cmprb,NORMAL,,1P,EXTRA3,NO,d:BF,s:RA,s:RB,0,RA,RB,0,0,0,BF,0 -cmpeqb,NORMAL,,1P,EXTRA3,NO,d:BF,s:RA,s:RB,0,RA,RB,0,0,0,BF,0 +cmp,CROP,,1P,EXTRA3,NO,d:BF,s:RA,s:RB,0,RA,RB,0,0,0,BF,0 +cmpl,CROP,,1P,EXTRA3,NO,d:BF,s:RA,s:RB,0,RA,RB,0,0,0,BF,0 +cmprb,CROP,,1P,EXTRA3,NO,d:BF,s:RA,s:RB,0,RA,RB,0,0,0,BF,0 +cmpeqb,CROP,,1P,EXTRA3,NO,d:BF,s:RA,s:RB,0,RA,RB,0,0,0,BF,0 0/0=fcmpu,NORMAL,,1P,EXTRA3,NO,d:BF,s:FRA,s:FRB,0,FRA,FRB,0,0,0,BF,0 1/0=fcmpo,NORMAL,,1P,EXTRA3,NO,d:BF,s:FRA,s:FRB,0,FRA,FRB,0,0,0,BF,0 4/0=ftdiv,NORMAL,,1P,EXTRA3,NO,d:BF,s:FRA,s:FRB,0,FRA,FRB,0,0,0,BF,0 @@ -18,7 +18,7 @@ bmask,NORMAL,,1P,EXTRA3,NO,d:RT,s:RA,s:RB,0,RA,RB,0,RT,0,0,0 bpermd,NORMAL,,1P,EXTRA3,NO,d:RA,s:RS,s:RB,0,RS,RB,0,RA,0,0,0 modud,NORMAL,,1P,EXTRA3,NO,d:RT,s:RA,s:RB,0,RA,RB,0,RT,0,0,0 moduw,NORMAL,,1P,EXTRA3,NO,d:RT,s:RA,s:RB,0,RA,RB,0,RT,0,0,0 -cmpb,NORMAL,,1P,EXTRA3,NO,d:RA,s:RS,s:RB,0,RS,RB,0,RA,0,0,0 +cmpb,CROP,,1P,EXTRA3,NO,d:RA,s:RS,s:RB,0,RS,RB,0,RA,0,0,0 modsd,NORMAL,,1P,EXTRA3,NO,d:RT,s:RA,s:RB,0,RA,RB,0,RT,0,0,0 modsw,NORMAL,,1P,EXTRA3,NO,d:RT,s:RA,s:RB,0,RA,RB,0,RT,0,0,0 26/6=fmrgow,NORMAL,,1P,EXTRA3,NO,d:FRT,s:FRA,s:FRB,0,FRA,FRB,0,FRT,0,0,0 diff --git a/openpower/isatables/RM-2P-1S1D.csv b/openpower/isatables/RM-2P-1S1D.csv index 1c0a2f8f..e2f314af 100644 --- a/openpower/isatables/RM-2P-1S1D.csv +++ b/openpower/isatables/RM-2P-1S1D.csv @@ -4,8 +4,8 @@ mfcr/mfocrf,NORMAL,,2P,EXTRA3,EN,d:RT,s:CR,0,0,0,0,0,RT,WHOLE_REG,0,0 setb,NORMAL,,2P,EXTRA3,EN,d:RT,s:BFA,0,0,0,0,0,RT,BFA,0,0 5/0=ftsqrt,NORMAL,,2P,EXTRA3,EN,d:BF,s:FRB,0,0,0,FRB,0,0,0,BF,0 22/7=mtfsf,NORMAL,,2P,EXTRA3,EN,d:CR1,s:FRB,0,0,0,FRB,0,0,0,CR1,0 -cmpli,NORMAL,,2P,EXTRA3,EN,d:BF,s:RA,0,0,RA,0,0,0,0,BF,0 -cmpi,NORMAL,,2P,EXTRA3,EN,d:BF,s:RA,0,0,RA,0,0,0,0,BF,0 +cmpli,CROP,,2P,EXTRA3,EN,d:BF,s:RA,0,0,RA,0,0,0,0,BF,0 +cmpi,CROP,,2P,EXTRA3,EN,d:BF,s:RA,0,0,RA,0,0,0,0,BF,0 neg,NORMAL,,2P,EXTRA3,EN,d:RT,s:RA,0,0,RA,0,0,RT,0,0,0 popcntb,NORMAL,,2P,EXTRA3,EN,d:RA,s:RS,0,0,RS,0,0,RA,0,0,0 prtyw,NORMAL,,2P,EXTRA3,EN,d:RA,s:RS,0,0,RS,0,0,RA,0,0,0 diff --git a/src/openpower/sv/sv_analysis.py b/src/openpower/sv/sv_analysis.py index 9b030098..332a0b2d 100644 --- a/src/openpower/sv/sv_analysis.py +++ b/src/openpower/sv/sv_analysis.py @@ -797,7 +797,7 @@ def process_csvs(format): mode = 'LDST_IMM' elif insn_name.startswith('bc'): mode = 'BRANCH' - elif insn_name.startswith('cr') or insn_name in crops: + elif insn_name.startswith('cmp') or insn_name.startswith('cr') or insn_name in crops: mode = 'CROP' res['mode'] = mode diff --git a/src/openpower/sv/trans/svp64.py b/src/openpower/sv/trans/svp64.py index 7a1a2d78..ea83f6a0 100644 --- a/src/openpower/sv/trans/svp64.py +++ b/src/openpower/sv/trans/svp64.py @@ -1059,8 +1059,9 @@ class SVP64Asm: is_ld = v30b_op.startswith("l") and is_ldst is_st = v30b_op.startswith("s") and is_ldst - # branch-conditional detection + # branch-conditional or CR detection is_bc = rm['mode'] == 'BRANCH' + is_cr = rm['mode'] == 'CROP' # parts of svp64_rm mmode = 0 # bit 0 @@ -1360,15 +1361,18 @@ class SVP64Asm: if failfirst == 'RC1': mode |= (0b1 << SVP64MODE.RC1) # sets RC1 mode mode |= (dst_zero << SVP64MODE.DZ) # predicate dst-zeroing - assert rc_mode == False, "ffirst RC1 only ok when Rc=0" + if not is_cr: + assert rc_mode == False, "ffirst RC1 only ok when Rc=0" elif failfirst == '~RC1': mode |= (0b1 << SVP64MODE.RC1) # sets RC1 mode mode |= (dst_zero << SVP64MODE.DZ) # predicate dst-zeroing mode |= (0b1 << SVP64MODE.INV) # ... with inversion - assert rc_mode == False, "ffirst RC1 only ok when Rc=0" + if not is_cr: + assert rc_mode == False, "ffirst RC1 only ok when Rc=0" else: assert dst_zero == 0, "dst-zero not allowed in ffirst BO" - assert rc_mode, "ffirst BO only possible when Rc=1" + if not is_cr: + assert rc_mode, "ffirst BO only possible when Rc=1" mode |= (failfirst << SVP64MODE.BO_LSB) # set BO ###################################### @@ -1714,6 +1718,9 @@ if __name__ == '__main__': 'sv.bc/all 3,12,192', 'pcdec. 0,0,0,0', ] + lst = [ + "sv.cmp/ff=gt *0,*1,*2,0", + ] isa = SVP64Asm(lst, macros=macros) log("list:\n", "\n\t".join(list(isa))) # running svp64.py is designed to test hard-coded lists diff --git a/src/openpower/sv/trans/test_pysvp64dis.py b/src/openpower/sv/trans/test_pysvp64dis.py index c71dfc77..95817cc0 100644 --- a/src/openpower/sv/trans/test_pysvp64dis.py +++ b/src/openpower/sv/trans/test_pysvp64dis.py @@ -304,6 +304,13 @@ class SVSTATETestCase(unittest.TestCase): ] self._do_tst(expected) + def test_20_cmp(self): + expected = [ + "sv.cmp *4,1,*0,1", + "sv.cmp/ff=RC1 *4,1,*0,1", + ] + self._do_tst(expected) + if __name__ == "__main__": unittest.main()