From: lkcl <lkcl@web>
Date: Fri, 28 Apr 2023 11:34:58 +0000 (+0100)
Subject: (no commit message)
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=092768c24051aa9be9a51d3981baddcd4226ecd7;p=libreriscv.git

---

diff --git a/openpower/sv/twin_butterfly.mdwn b/openpower/sv/twin_butterfly.mdwn
index 8e0066801..c70a48c6b 100644
--- a/openpower/sv/twin_butterfly.mdwn
+++ b/openpower/sv/twin_butterfly.mdwn
@@ -73,3 +73,32 @@ The instruction has been added to `minor_22.csv`:
 ------01000,ALU,OP_MADDSUBRS,RT,CONST_SH,RB,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC_ONLY,0,0,maddsubrs,A,,1,unofficial until submitted and approved/renumbered by the opf isa wg
 ```
 
+
+# [DRAFT] Floating Twin Multiply-Add DCT [Single]
+
+DCT-Form
+
+```
+    |0     |6     |11      |16     |21      |26    |31 |
+    | PO   |  FRT |   FRA  |   FRB |   //   |   XO |Rc |
+```
+
+* fdmadds FRT,FRA,FRB (Rc=0)
+* fdmadds. FRT,FRA,FRB (Rc=1)
+
+Pseudo-code:
+
+```
+    FRS <- FPADD32(FRT, FRB)
+    sub <- FPSUB32(FRT, FRB)
+    FRT <- FPMUL32(FRA, sub)
+```
+
+Special Registers Altered:
+
+```
+    FPRF FR FI
+    FX OX UX XX
+    VXSNAN VXISI VXIMZ
+    CR1          (if Rc=1)
+```