From: Marek Olšák <marek.olsak@amd.com>
Date: Wed, 11 Mar 2020 00:46:16 +0000 (-0400)
Subject: radeonsi: tune primitive binning for small chips
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=09295e95eba6f015d1731b589070cf5bbef3d581;p=mesa.git

radeonsi: tune primitive binning for small chips

same as PAL

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4143>
---

diff --git a/src/gallium/drivers/radeonsi/si_state_binning.c b/src/gallium/drivers/radeonsi/si_state_binning.c
index aae18f03636..1251b53785b 100644
--- a/src/gallium/drivers/radeonsi/si_state_binning.c
+++ b/src/gallium/drivers/radeonsi/si_state_binning.c
@@ -485,7 +485,8 @@ void si_emit_dpbb_state(struct si_context *sctx)
 		G_02880C_DEPTH_BEFORE_SHADER(db_shader_control);
 
 	/* Disable DPBB when it's believed to be inefficient. */
-	if (ps_can_kill &&
+	if (sscreen->info.num_render_backends > 4 &&
+	    ps_can_kill &&
 	    db_can_reject_z_trivially &&
 	    sctx->framebuffer.state.zsbuf &&
 	    dsa->db_can_write) {
@@ -546,8 +547,13 @@ void si_emit_dpbb_state(struct si_context *sctx)
 
 	/* Tuned for Raven. Vega might need different values. */
 	if (sscreen->info.has_dedicated_vram) {
-		context_states_per_bin = 1;
-		persistent_states_per_bin = 1;
+		if (sscreen->info.num_render_backends > 4) {
+			context_states_per_bin = 1;
+			persistent_states_per_bin = 1;
+		} else {
+			context_states_per_bin = 3;
+			persistent_states_per_bin = 8;
+		}
 	} else {
 		/* This is a workaround for:
 		 *    https://bugs.freedesktop.org/show_bug.cgi?id=110214