From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 18 Jul 2019 22:38:28 +0000 (-0700)
Subject: ice40_dsp to accept $__MUL16X16 too
X-Git-Tag: working-ls180~1039^2~331
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=09411dd996f75dbce22a6f6979b7d61b0dae24f7;p=yosys.git

ice40_dsp to accept $__MUL16X16 too
---

diff --git a/passes/pmgen/ice40_dsp.pmg b/passes/pmgen/ice40_dsp.pmg
index 1f3590d4e..f2b7f2169 100644
--- a/passes/pmgen/ice40_dsp.pmg
+++ b/passes/pmgen/ice40_dsp.pmg
@@ -6,7 +6,7 @@ state <SigSpec> sigA sigB sigY sigS
 state <Cell*> addAB muxAB
 
 match mul
-	select mul->type.in($mul)
+	select mul->type.in($mul, $__MUL16X16)
 	select GetSize(mul->getPort(\A)) + GetSize(mul->getPort(\B)) > 10
 	select GetSize(mul->getPort(\Y)) > 10
 endmatch