From: Clifford Wolf <clifford@clifford.at>
Date: Tue, 7 May 2019 13:04:36 +0000 (+0200)
Subject: Add "synth_xilinx -arch"
X-Git-Tag: yosys-0.9~139
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=09467bb9a3ca01bb7bbfc6c9013ed7385e42fd96;p=yosys.git

Add "synth_xilinx -arch"

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---

diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index 8aa7b508e..b022972c9 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -42,6 +42,10 @@ struct SynthXilinxPass : public ScriptPass
 		log("    -top <module>\n");
 		log("        use the specified module as top module\n");
 		log("\n");
+		log("    -arch {xcup|xcu|xc7|xc6s}\n");
+		log("        run synthesis for the specified Xilinx architecture\n");
+		log("        default: xc7\n");
+		log("\n");
 		log("    -edif <file>\n");
 		log("        write the design to the specified edif file. writing of an output file\n");
 		log("        is omitted if this parameter is not specified.\n");
@@ -80,7 +84,7 @@ struct SynthXilinxPass : public ScriptPass
 		log("\n");
 	}
 
-	std::string top_opt, edif_file, blif_file;
+	std::string top_opt, edif_file, blif_file, arch;
 	bool flatten, retime, vpr, nobram, nodram, nosrl;
 
 	void clear_flags() YS_OVERRIDE
@@ -94,6 +98,7 @@ struct SynthXilinxPass : public ScriptPass
 		nobram = false;
 		nodram = false;
 		nosrl = false;
+		arch = "xc7";
 	}
 
 	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
@@ -108,6 +113,10 @@ struct SynthXilinxPass : public ScriptPass
 				top_opt = "-top " + args[++argidx];
 				continue;
 			}
+			if (args[argidx] == "-arch" && argidx+1 < args.size()) {
+				arch = args[++argidx];
+				continue;
+			}
 			if (args[argidx] == "-edif" && argidx+1 < args.size()) {
 				edif_file = args[++argidx];
 				continue;
@@ -152,6 +161,9 @@ struct SynthXilinxPass : public ScriptPass
 		}
 		extra_args(args, argidx, design);
 
+		if (arch != "xcup" && arch != "xcu" && arch != "xc7" && arch != "xc6s")
+			log_cmd_error("Invalid Xilinx -arch setting: %s\n", arch.c_str());
+
 		if (!design->full_selection())
 			log_cmd_error("This command only operates on fully selected designs!\n");