From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Tue, 21 Jul 2020 09:41:36 +0000 (+0100)
Subject: correct trap spec page interrupt ref
X-Git-Tag: semi_working_ecp5~662
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=0949e113f0979adb56e1e8af4106d39bfd56b55f;p=soc.git

correct trap spec page interrupt ref
---

diff --git a/src/soc/fu/trap/main_stage.py b/src/soc/fu/trap/main_stage.py
index 39f4326d..37ea4af2 100644
--- a/src/soc/fu/trap/main_stage.py
+++ b/src/soc/fu/trap/main_stage.py
@@ -150,7 +150,7 @@ class TrapMainStage(PipeModBase):
                     # generate trap-type program interrupt
                     self.trap(m, trapaddr<<4, cia_i)
                     with m.If(traptype == 0):
-                        # say trap occurred (see 3.0B Book III 7.5.9)
+                        # say trap occurred (see 3.0B Book III 6.5.9 p1074-6)
                         comb += srr1_o.data[PI.TRAP].eq(1)
                     with m.If(traptype & TT.PRIV):
                         comb += srr1_o.data[PI.PRIV].eq(1)