From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Thu, 18 Jun 2020 10:29:29 +0000 (+0100)
Subject: use different way to pass instructions to test_issuer ISACaller
X-Git-Tag: div_pipeline~329^2~2
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=094a886d36fbe6a924ae92cba5adc583d9e058df;p=soc.git

use different way to pass instructions to test_issuer ISACaller
---

diff --git a/src/soc/simple/test/test_issuer.py b/src/soc/simple/test/test_issuer.py
index 953525e3..f5fc6dc8 100644
--- a/src/soc/simple/test/test_issuer.py
+++ b/src/soc/simple/test/test_issuer.py
@@ -81,10 +81,13 @@ class TestRunner(FHDLTestCase):
                 print ("mem", test.mem)
                 print ("msr", test.msr)
                 print ("assem", program.assembly)
-                sim = ISA(pdecode2, test.regs, test.sprs, test.cr, test.mem,
-                          test.msr)
                 gen = list(program.generate_instructions())
-                instructions = list(zip(gen, program.assembly.splitlines()))
+                insncode = program.assembly.splitlines()
+                instructions = list(zip(gen, insncode))
+                sim = ISA(pdecode2, test.regs, test.sprs, test.cr, test.mem,
+                          test.msr,
+                          initial_insns=gen, respect_pc=True,
+                          disassembly=insncode)
 
                 pc = 0 # start address