From: Cesar Strauss <cestrauss@gmail.com>
Date: Wed, 3 Jun 2020 01:28:56 +0000 (-0300)
Subject: Simplify immediate check
X-Git-Tag: div_pipeline~637^2~17
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=0956cf0692ed1487bcb0a643d344158cf052c440;p=soc.git

Simplify immediate check
---

diff --git a/src/soc/experiment/test/test_compalu_multi.py b/src/soc/experiment/test/test_compalu_multi.py
index 8796a610..64b8daec 100644
--- a/src/soc/experiment/test/test_compalu_multi.py
+++ b/src/soc/experiment/test/test_compalu_multi.py
@@ -137,6 +137,7 @@ class CompUnitParallelTest:
         self.op = 0
         self.inv_a = self.zero_a = 0
         self.imm = self.imm_ok = 0
+        self.imm_control = (0, 0)
         self.rdmaskn = (0, 0)
         # input data:
         self.operands = (0, 0)
@@ -155,6 +156,7 @@ class CompUnitParallelTest:
         self.imm = imm
         self.imm_ok = imm_ok
         self.zero_a = zero_a
+        self.imm_control = (zero_a, imm_ok)
         self.rdmaskn = rdmaskn
 
         # trigger operation cycle
@@ -245,9 +247,7 @@ class CompUnitParallelTest:
         # likewise, if the read mask is active
         # TODO: don't exit the process, monitor rd instead to ensure it
         #       doesn't rise on its own
-        if self.rdmaskn[rd_idx] \
-                or (rd_idx == 0 and self.zero_a) \
-                or (rd_idx == 1 and self.imm_ok):
+        if self.rdmaskn[rd_idx] or self.imm_control[rd_idx]:
             return
 
         # issue_i has risen. rel must rise on the next cycle