From: Dave Airlie Date: Thu, 28 Dec 2017 22:52:07 +0000 (+1000) Subject: radv/gfx9: fix 3d image clears on compute queues X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=09612a62e169c7d918e6578408166c1f32db8bc4;p=mesa.git radv/gfx9: fix 3d image clears on compute queues This fixes some of the broken: dEQP-VK.synchronization.op.multi_queue.*64x64x8* tests. Fixes: e38685cc62e 'Revert "radv: disable support for VEGA for now."' Reviewed-by: Bas Nieuwenhuizen Signed-off-by: Dave Airlie --- diff --git a/src/amd/vulkan/radv_meta_bufimage.c b/src/amd/vulkan/radv_meta_bufimage.c index b2dca80ad50..1696f85ac16 100644 --- a/src/amd/vulkan/radv_meta_bufimage.c +++ b/src/amd/vulkan/radv_meta_bufimage.c @@ -667,15 +667,16 @@ radv_device_finish_meta_itoi_state(struct radv_device *device) } static nir_shader * -build_nir_cleari_compute_shader(struct radv_device *dev) +build_nir_cleari_compute_shader(struct radv_device *dev, bool is_3d) { nir_builder b; - const struct glsl_type *img_type = glsl_sampler_type(GLSL_SAMPLER_DIM_2D, + enum glsl_sampler_dim dim = is_3d ? GLSL_SAMPLER_DIM_3D : GLSL_SAMPLER_DIM_2D; + const struct glsl_type *img_type = glsl_sampler_type(dim, false, false, GLSL_TYPE_FLOAT); nir_builder_init_simple_shader(&b, NULL, MESA_SHADER_COMPUTE, NULL); - b.shader->info.name = ralloc_strdup(b.shader, "meta_cleari_cs"); + b.shader->info.name = ralloc_strdup(b.shader, is_3d ? "meta_cleari_cs_3d" : "meta_cleari_cs"); b.shader->info.cs.local_size[0] = 16; b.shader->info.cs.local_size[1] = 16; b.shader->info.cs.local_size[2] = 1; @@ -696,12 +697,29 @@ build_nir_cleari_compute_shader(struct radv_device *dev) nir_intrinsic_instr *clear_val = nir_intrinsic_instr_create(b.shader, nir_intrinsic_load_push_constant); nir_intrinsic_set_base(clear_val, 0); - nir_intrinsic_set_range(clear_val, 16); + nir_intrinsic_set_range(clear_val, 20); clear_val->src[0] = nir_src_for_ssa(nir_imm_int(&b, 0)); clear_val->num_components = 4; nir_ssa_dest_init(&clear_val->instr, &clear_val->dest, 4, 32, "clear_value"); nir_builder_instr_insert(&b, &clear_val->instr); + nir_intrinsic_instr *layer = nir_intrinsic_instr_create(b.shader, nir_intrinsic_load_push_constant); + nir_intrinsic_set_base(layer, 0); + nir_intrinsic_set_range(layer, 20); + layer->src[0] = nir_src_for_ssa(nir_imm_int(&b, 16)); + layer->num_components = 1; + nir_ssa_dest_init(&layer->instr, &layer->dest, 1, 32, "layer"); + nir_builder_instr_insert(&b, &layer->instr); + + nir_ssa_def *global_z = nir_iadd(&b, nir_channel(&b, global_id, 2), &layer->dest.ssa); + + nir_ssa_def *comps[4]; + comps[0] = nir_channel(&b, global_id, 0); + comps[1] = nir_channel(&b, global_id, 1); + comps[2] = global_z; + comps[3] = nir_imm_int(&b, 0); + global_id = nir_vec(&b, comps, 4); + nir_intrinsic_instr *store = nir_intrinsic_instr_create(b.shader, nir_intrinsic_image_store); store->src[0] = nir_src_for_ssa(global_id); store->src[1] = nir_src_for_ssa(nir_ssa_undef(&b, 1, 32)); @@ -717,8 +735,10 @@ radv_device_init_meta_cleari_state(struct radv_device *device) { VkResult result; struct radv_shader_module cs = { .nir = NULL }; - - cs.nir = build_nir_cleari_compute_shader(device); + struct radv_shader_module cs_3d = { .nir = NULL }; + cs.nir = build_nir_cleari_compute_shader(device, false); + if (device->physical_device->rad_info.chip_class >= GFX9) + cs_3d.nir = build_nir_cleari_compute_shader(device, true); /* * two descriptors one for the image being sampled @@ -752,7 +772,7 @@ radv_device_init_meta_cleari_state(struct radv_device *device) .setLayoutCount = 1, .pSetLayouts = &device->meta_state.cleari.img_ds_layout, .pushConstantRangeCount = 1, - .pPushConstantRanges = &(VkPushConstantRange){VK_SHADER_STAGE_COMPUTE_BIT, 0, 16}, + .pPushConstantRanges = &(VkPushConstantRange){VK_SHADER_STAGE_COMPUTE_BIT, 0, 20}, }; result = radv_CreatePipelineLayout(radv_device_to_handle(device), @@ -786,10 +806,38 @@ radv_device_init_meta_cleari_state(struct radv_device *device) if (result != VK_SUCCESS) goto fail; + + if (device->physical_device->rad_info.chip_class >= GFX9) { + /* compute shader */ + VkPipelineShaderStageCreateInfo pipeline_shader_stage_3d = { + .sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO, + .stage = VK_SHADER_STAGE_COMPUTE_BIT, + .module = radv_shader_module_to_handle(&cs_3d), + .pName = "main", + .pSpecializationInfo = NULL, + }; + + VkComputePipelineCreateInfo vk_pipeline_info_3d = { + .sType = VK_STRUCTURE_TYPE_COMPUTE_PIPELINE_CREATE_INFO, + .stage = pipeline_shader_stage_3d, + .flags = 0, + .layout = device->meta_state.cleari.img_p_layout, + }; + + result = radv_CreateComputePipelines(radv_device_to_handle(device), + radv_pipeline_cache_to_handle(&device->meta_state.cache), + 1, &vk_pipeline_info_3d, NULL, + &device->meta_state.cleari.pipeline_3d); + if (result != VK_SUCCESS) + goto fail; + + ralloc_free(cs_3d.nir); + } ralloc_free(cs.nir); return VK_SUCCESS; fail: ralloc_free(cs.nir); + ralloc_free(cs_3d.nir); return result; } @@ -805,6 +853,8 @@ radv_device_finish_meta_cleari_state(struct radv_device *device) &state->alloc); radv_DestroyPipeline(radv_device_to_handle(device), state->cleari.pipeline, &state->alloc); + radv_DestroyPipeline(radv_device_to_handle(device), + state->cleari.pipeline_3d, &state->alloc); } void @@ -1163,19 +1213,24 @@ radv_meta_clear_image_cs(struct radv_cmd_buffer *cmd_buffer, create_iview(cmd_buffer, dst, &dst_iview); cleari_bind_descriptors(cmd_buffer, &dst_iview); + if (device->physical_device->rad_info.chip_class >= GFX9 && + dst->image->type == VK_IMAGE_TYPE_3D) + pipeline = cmd_buffer->device->meta_state.cleari.pipeline_3d; + radv_CmdBindPipeline(radv_cmd_buffer_to_handle(cmd_buffer), VK_PIPELINE_BIND_POINT_COMPUTE, pipeline); - unsigned push_constants[4] = { + unsigned push_constants[5] = { clear_color->uint32[0], clear_color->uint32[1], clear_color->uint32[2], clear_color->uint32[3], + dst->layer, }; radv_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer), device->meta_state.cleari.img_p_layout, - VK_SHADER_STAGE_COMPUTE_BIT, 0, 16, + VK_SHADER_STAGE_COMPUTE_BIT, 0, 20, push_constants); radv_unaligned_dispatch(cmd_buffer, dst->image->info.width, dst->image->info.height, 1); diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h index a8270483014..05ad480c578 100644 --- a/src/amd/vulkan/radv_private.h +++ b/src/amd/vulkan/radv_private.h @@ -449,6 +449,7 @@ struct radv_meta_state { VkPipelineLayout img_p_layout; VkDescriptorSetLayout img_ds_layout; VkPipeline pipeline; + VkPipeline pipeline_3d; } cleari; struct {