From: argama <argama@gmail.com>
Date: Tue, 16 Oct 2018 13:33:37 +0000 (+0800)
Subject: ignore protect endprotect
X-Git-Tag: yosys-0.9~442^2
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=097da32e1a8cfe29d64666c1b2c9b47129b07c7e;p=yosys.git

ignore protect endprotect
---

diff --git a/frontends/verilog/verilog_lexer.l b/frontends/verilog/verilog_lexer.l
index 83921bf0b..2c4880b84 100644
--- a/frontends/verilog/verilog_lexer.l
+++ b/frontends/verilog/verilog_lexer.l
@@ -135,6 +135,9 @@ YOSYS_NAMESPACE_END
 		frontend_verilog_yyerror("Unsupported default nettype: %s", p);
 }
 
+"`protect"[^\n]* /* ignore `protect*/
+"`endprotect"[^\n]* /* ignore `endprotect*/
+
 "`"[a-zA-Z_$][a-zA-Z0-9_$]* {
 	frontend_verilog_yyerror("Unimplemented compiler directive or undefined macro %s.", yytext);
 }