From: Jeff Law Date: Wed, 25 Feb 1998 08:58:23 +0000 (+0000) Subject: * simops.c (signed multiply instructions): Cast input operands to X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=097e6924c2d28d8171eaa4665b9dab9e63c8a967;p=binutils-gdb.git * simops.c (signed multiply instructions): Cast input operands to signed32 before casting them to signed64 so that the sign bit is propagated properly. --- diff --git a/sim/mn10300/ChangeLog b/sim/mn10300/ChangeLog index ad4abf2aca4..cc4a1b57334 100644 --- a/sim/mn10300/ChangeLog +++ b/sim/mn10300/ChangeLog @@ -1,3 +1,9 @@ +Wed Feb 25 01:59:29 1998 Jeffrey A Law (law@cygnus.com) + + * simops.c (signed multiply instructions): Cast input operands to + signed32 before casting them to signed64 so that the sign bit + is propagated properly. + Mon Feb 23 20:23:19 1998 Mark Alexander * Makefile.in: Last change was bad. Define NL_TARGET diff --git a/sim/mn10300/simops.c b/sim/mn10300/simops.c index efed7dcc99e..6425e497229 100644 --- a/sim/mn10300/simops.c +++ b/sim/mn10300/simops.c @@ -1433,8 +1433,8 @@ void OP_F240 (insn, extension) unsigned long long temp; int n, z; - temp = ((signed64)State.regs[REG_D0 + REG0 (insn)] - * (signed64)State.regs[REG_D0 + REG1 (insn)]); + temp = ((signed64)(signed32)State.regs[REG_D0 + REG0 (insn)] + * (signed64)(signed32)State.regs[REG_D0 + REG1 (insn)]); State.regs[REG_D0 + REG0 (insn)] = temp & 0xffffffff; State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;; z = (State.regs[REG_D0 + REG0 (insn)] == 0); @@ -3061,8 +3061,8 @@ void OP_F600 (insn, extension) unsigned long long temp; int n, z; - temp = ((signed64)State.regs[REG_D0 + REG0 (insn)] - * (signed64)State.regs[REG_D0 + REG1 (insn)]); + temp = ((signed64)(signed32)State.regs[REG_D0 + REG0 (insn)] + * (signed64)(signed32)State.regs[REG_D0 + REG1 (insn)]); State.regs[REG_D0 + REG0 (insn)] = temp & 0xffffffff; State.regs[REG_MDRQ] = (temp & 0xffffffff00000000LL) >> 32;; z = (State.regs[REG_D0 + REG0 (insn)] == 0); @@ -3078,8 +3078,8 @@ void OP_F90000 (insn, extension) unsigned long long temp; int n, z; - temp = ((signed64)State.regs[REG_D0 + REG0_8 (insn)] - * (signed64)SEXT8 (insn & 0xff)); + temp = ((signed64)(signed32)State.regs[REG_D0 + REG0_8 (insn)] + * (signed64)(signed32)SEXT8 (insn & 0xff)); State.regs[REG_D0 + REG0_8 (insn)] = temp & 0xffffffff; State.regs[REG_MDRQ] = (temp & 0xffffffff00000000LL) >> 32;; z = (State.regs[REG_D0 + REG0_8 (insn)] == 0); @@ -3095,8 +3095,8 @@ void OP_FB000000 (insn, extension) unsigned long long temp; int n, z; - temp = ((signed64)State.regs[REG_D0 + REG0_16 (insn)] - * (signed64)SEXT16 (insn & 0xffff)); + temp = ((signed64)(signed32)State.regs[REG_D0 + REG0_16 (insn)] + * (signed64)(signed32)SEXT16 (insn & 0xffff)); State.regs[REG_D0 + REG0_16 (insn)] = temp & 0xffffffff; State.regs[REG_MDRQ] = (temp & 0xffffffff00000000LL) >> 32;; z = (State.regs[REG_D0 + REG0_16 (insn)] == 0); @@ -3112,8 +3112,8 @@ void OP_FD000000 (insn, extension) unsigned long long temp; int n, z; - temp = ((signed64)State.regs[REG_D0 + REG0_16 (insn)] - * (signed64)(((insn & 0xffff) << 16) + extension)); + temp = ((signed64)(signed32)State.regs[REG_D0 + REG0_16 (insn)] + * (signed64)(signed32)(((insn & 0xffff) << 16) + extension)); State.regs[REG_D0 + REG0_16 (insn)] = temp & 0xffffffff; State.regs[REG_MDRQ] = (temp & 0xffffffff00000000LL) >> 32;; z = (State.regs[REG_D0 + REG0_16 (insn)] == 0);