From: Luke Kenneth Casson Leighton Date: Sat, 29 Jun 2019 07:45:15 +0000 (+0100) Subject: immed in same 6 bits X-Git-Tag: convert-csv-opcode-to-binary~4349 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=09818820825e3f610e5f5a7f048932a02bf052b2;p=libreriscv.git immed in same 6 bits --- diff --git a/simple_v_extension/vblock_format_table.mdwn b/simple_v_extension/vblock_format_table.mdwn index d381ede9f..97b812092 100644 --- a/simple_v_extension/vblock_format_table.mdwn +++ b/simple_v_extension/vblock_format_table.mdwn @@ -14,10 +14,10 @@ of the RISC-V ISA, is as follows: The VL/MAXVL/SubVL Block format: [[!table data=""" -31:30 | 29:28 | 27:22 | 21:19 | 18:16 | comment | -0b00 | SubVL | VLdest | imm[5:0] || VL set from imm | -0b01 | SubVL | MVLimm | rs1[2:0] | rd[2:0] | RVC reg format | -0b10 | SubVL | VLdest | imm[5:0] || VL & MVL set from imm| -0b11 | rsvd | rsvd | rsvd | rsvd | reserved, all 0s | +31:30 | 29:28 | 27:22 | 21 | 20:19 | 18:16 | comment | +0b00 | SubVL |imm[5:0]|rsvd| rd[4:0] || VL set from imm | +0b01 | SubVL |imm[5:0]| rs1[2:0] || rd[2:0] | RVC reg format | +0b10 | SubVL |imm[5:0]|rsvd| rd[4:0] || VL & MVL set from imm| +0b11 | rsvd | rsvd |rsvd| rsvd || reserved, all 0s | """]]