From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 3 May 2019 22:35:26 +0000 (-0700)
Subject: Add quick-and-dirty specify tests
X-Git-Tag: yosys-0.9~141^2~7
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=09841c2ac1f36d06faada27093a2cf0cdfb6cb42;p=yosys.git

Add quick-and-dirty specify tests
---

diff --git a/tests/various/specify.v b/tests/various/specify.v
new file mode 100644
index 000000000..aea0d0fc5
--- /dev/null
+++ b/tests/various/specify.v
@@ -0,0 +1,28 @@
+module test (
+	input EN, CLK,
+	input [3:0] D,
+	output reg [3:0] Q
+);
+	always @(posedge CLK)
+		if (EN) Q <= D;
+
+	specify
+		if (EN) (CLK *> (Q : D)) = (1, 2:3:4);
+		$setup(D, posedge CLK &&& EN, 5);
+		$hold(posedge CLK, D &&& EN, 6);
+	endspecify
+endmodule
+
+module test2 (
+    input A, B,
+	output Q
+);
+    xor (Q, A, B);
+	specify
+		//specparam T_rise = 1;
+        //specparam T_fall = 2;
+        `define T_rise 1
+        `define T_fall 2
+        (A => Q) = (`T_rise,`T_fall);
+	endspecify
+endmodule
diff --git a/tests/various/specify.ys b/tests/various/specify.ys
new file mode 100644
index 000000000..c4e901705
--- /dev/null
+++ b/tests/various/specify.ys
@@ -0,0 +1,25 @@
+read_verilog -specify specify.v
+prep
+cd test
+select t:$specify2 -assert-count 0
+select t:$specify3 -assert-count 1
+select t:$specrule -assert-count 2
+cd test2
+select t:$specify2 -assert-count 1
+select t:$specify3 -assert-count 0
+select t:$specrule -assert-count 0
+write_verilog specify.out
+design -stash gold
+
+read_verilog -specify specify.out
+cd test
+select t:$specify2 -assert-count 0
+select t:$specify3 -assert-count 1
+select t:$specrule -assert-count 2
+cd test2
+select t:$specify2 -assert-count 1
+select t:$specify3 -assert-count 0
+select t:$specrule -assert-count 0
+design -stash gate
+
+# TODO: How to check $specify and $specrule-s are equivalent?