From: Sebastien Bourdeauducq <sb@m-labs.hk>
Date: Mon, 19 Oct 2015 11:17:26 +0000 (+0800)
Subject: verilog, sim: accept iterables in FHDL statements
X-Git-Tag: 24jan2021_ls180~2099^2~3^2~15
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=0999a173190c5bbfdb95cc493a0df4cc6a64460e;p=litex.git

verilog, sim: accept iterables in FHDL statements
---

diff --git a/migen/fhdl/verilog.py b/migen/fhdl/verilog.py
index 259899b9..72888999 100644
--- a/migen/fhdl/verilog.py
+++ b/migen/fhdl/verilog.py
@@ -1,5 +1,6 @@
 from functools import partial
 from operator import itemgetter
+import collections
 
 from migen.fhdl.structure import *
 from migen.fhdl.structure import _Operator, _Slice, _Assign, _Fragment
@@ -128,7 +129,7 @@ def _printnode(ns, at, level, node):
         else:
             assignment = " <= "
         return "\t"*level + _printexpr(ns, node.l)[0] + assignment + _printexpr(ns, node.r)[0] + ";\n"
-    elif isinstance(node, (list, tuple)):
+    elif isinstance(node, collections.Iterable):
         return "".join(list(map(partial(_printnode, ns, at, level), node)))
     elif isinstance(node, If):
         r = "\t"*level + "if (" + _printexpr(ns, node.cond)[0] + ") begin\n"
diff --git a/migen/sim/core.py b/migen/sim/core.py
index af3f3734..4c30c39a 100644
--- a/migen/sim/core.py
+++ b/migen/sim/core.py
@@ -1,4 +1,5 @@
 import operator
+import collections
 
 from migen.fhdl.structure import *
 from migen.fhdl.structure import (_Value, _Statement,
@@ -193,7 +194,7 @@ class Evaluator:
                         return
                 if "default" in s.cases:
                     self.execute(s.cases["default"])
-            elif isinstance(s, list):
+            elif isinstance(s, collections.Iterable):
                 self.execute(s)
             else:
                 raise NotImplementedError