From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Wed, 25 Mar 2020 17:56:58 +0000 (+0100)
Subject: integration/soc/add_uart: add Model/Sim.
X-Git-Tag: 24jan2021_ls180~517
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=09a3ce0ee5871588e0ba578d67b5e990da991588;p=litex.git

integration/soc/add_uart: add Model/Sim.
---

diff --git a/litex/soc/integration/soc.py b/litex/soc/integration/soc.py
index 91d44602..53684fdf 100644
--- a/litex/soc/integration/soc.py
+++ b/litex/soc/integration/soc.py
@@ -931,6 +931,13 @@ class LiteXSoC(SoC):
         elif name in ["crossover"]:
             self.submodules.uart = uart.UARTCrossover()
 
+        # Model/Sim
+        elif name in ["model", "sim"]:
+            self.submodules.uart_phy = uart.RS232PHYModel(self.platform.request("serial"))
+            self.submodules.uart = ResetInserter()(uart.UART(self.uart_phy,
+                tx_fifo_depth = fifo_depth,
+                rx_fifo_depth = fifo_depth))
+
         # JTAG Atlantic
         elif name in ["jtag_atlantic"]:
             from litex.soc.cores.jtag import JTAGAtlantic