From: Paul Mackerras Date: Mon, 15 Jun 2020 00:02:14 +0000 (+1000) Subject: decode1: Improve timing for slow SPR decode path X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=09ae2ce58d71f0901e22f8f1f82607b77f38443f;p=microwatt.git decode1: Improve timing for slow SPR decode path This makes the logic that works out decode.unit and decode.sgl_pipe for mtspr/mfspr to/from slow SPRs detect the fact that the instruction is mtspr/mfspr based on a match with the instruction word rather than looking at v.decode.insn_type. This improves timing substantially, as the ROM lookup to get v.decode is relatively slow. Signed-off-by: Paul Mackerras --- diff --git a/decode1.vhdl b/decode1.vhdl index 21596f6..f72d310 100644 --- a/decode1.vhdl +++ b/decode1.vhdl @@ -419,6 +419,20 @@ begin sprn := decode_spr_num(f_in.insn); v.ispr1 := fast_spr_num(sprn); + if std_match(f_in.insn(10 downto 1), "01-1010011") then + -- mfspr or mtspr + -- Make slow SPRs single issue + if is_fast_spr(v.ispr1) = '0' then + v.decode.sgl_pipe := '1'; + -- send MMU-related SPRs to loadstore1 + case sprn is + when SPR_DAR | SPR_DSISR | SPR_PID | SPR_PRTBL => + v.decode.unit := LDST; + when others => + end case; + end if; + end if; + elsif majorop = "010000" then -- CTR may be needed as input to bc v.decode := major_decode_rom_array(to_integer(majorop)); @@ -475,20 +489,6 @@ begin end if; - if v.decode.insn_type = OP_MFSPR or v.decode.insn_type = OP_MTSPR then - sprn := decode_spr_num(f_in.insn); - -- Make slow SPRs single issue - if is_fast_spr(v.ispr1) = '0' then - v.decode.sgl_pipe := '1'; - -- send MMU-related SPRs to loadstore1 - case sprn is - when SPR_DAR | SPR_DSISR | SPR_PID | SPR_PRTBL => - v.decode.unit := LDST; - when others => - end case; - end if; - end if; - -- Update registers rin <= v;