From: Gabe Black <gabeblack@google.com>
Date: Tue, 5 Nov 2019 23:53:02 +0000 (-0800)
Subject: fastmodel: Checkpoint the TCs when checkpointing a fast model CPU.
X-Git-Tag: v19.0.0.0~158
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=09b658f69969ef998b5994156f92f7b645aaf619;p=gem5.git

fastmodel: Checkpoint the TCs when checkpointing a fast model CPU.

The generic thread context checkpointing code can be used which calls
into the ThreadContext methods to read the required state.

Change-Id: Ib5c318ff4d2e756274b4c90b56533b2689a837f2
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23785
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
---

diff --git a/src/arch/arm/fastmodel/iris/cpu.cc b/src/arch/arm/fastmodel/iris/cpu.cc
index e5d95ef65..6c282b69a 100644
--- a/src/arch/arm/fastmodel/iris/cpu.cc
+++ b/src/arch/arm/fastmodel/iris/cpu.cc
@@ -31,6 +31,7 @@
 
 #include "arch/arm/fastmodel/iris/thread_context.hh"
 #include "scx/scx.h"
+#include "sim/serialize.hh"
 
 namespace Iris
 {
@@ -93,4 +94,10 @@ BaseCPU::init()
         tc->initMemProxies(tc);
 }
 
+void
+BaseCPU::serializeThread(CheckpointOut &cp, ThreadID tid) const
+{
+    ::serialize(*threadContexts[tid], cp);
+}
+
 } // namespace Iris
diff --git a/src/arch/arm/fastmodel/iris/cpu.hh b/src/arch/arm/fastmodel/iris/cpu.hh
index 0d15fc82a..3b913b92d 100644
--- a/src/arch/arm/fastmodel/iris/cpu.hh
+++ b/src/arch/arm/fastmodel/iris/cpu.hh
@@ -118,6 +118,8 @@ class BaseCPU : public ::BaseCPU
     }
 
     void init() override;
+
+    void serializeThread(CheckpointOut &cp, ThreadID tid) const override;
 };
 
 // This class specializes the one above and sets up ThreadContexts based on