From: lkcl <lkcl@web>
Date: Wed, 4 Aug 2021 09:33:40 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: DRAFT_SVP64_0_1~511
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=09ba7153714c1850ba6cd2ee40570099c3bf4bcf;p=libreriscv.git

---

diff --git a/openpower/sv/overview.mdwn b/openpower/sv/overview.mdwn
index ca6aacdc5..f90aca7f7 100644
--- a/openpower/sv/overview.mdwn
+++ b/openpower/sv/overview.mdwn
@@ -909,6 +909,18 @@ implementations may cause pipeline stalls.  This was one of the reasons
 why CR-based pred-result analysis was added, because that at least is
 entirely paralleliseable.
 
+# Vertical-First Mode
+
+This is a relatively new addition to SVP64 under development as of
+July 2021.  Where Horizontal-First is the standard Cray-style for-loop,
+Vertical-First typically executes just the **one** scalar element
+in each Vectorised operation. That element is selected by srcstep
+and dststep *neither of which are changed as a side-effect of execution*.
+
+To create loops, either a new instruction `svstep` must be called,
+explicitly, or [[sv/branches]] must be given a mode bit to request
+explicit incrementation of srcstep and dststep.
+
 # Instruction format
 
 Whilst this overview shows the internals, it does not go into detail