From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Mon, 25 May 2020 18:45:55 +0000 (+0100)
Subject: update comments on compalu_multi.py
X-Git-Tag: div_pipeline~827
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=09bd372c8e1f2f98b4edd7e89fdd8798f628bcb8;p=soc.git

update comments on compalu_multi.py
---

diff --git a/src/soc/experiment/compalu_multi.py b/src/soc/experiment/compalu_multi.py
index 355b78bb..2764f76b 100644
--- a/src/soc/experiment/compalu_multi.py
+++ b/src/soc/experiment/compalu_multi.py
@@ -419,13 +419,13 @@ class CompUnitParallelTest:
         # monitor self.dut.rd.req[rd_idx] and sets dut.rd.go[idx] for one cycle
         yield
         # TODO: also when dut.rd.go is set, put the expected value into
-        # the src_i.
+        # the src_i.  use dut.get_in[rd_idx] to do so
 
     def wr(self, wr_idx):
         # monitor self.dut.wr.req[rd_idx] and sets dut.wr.go[idx] for one cycle
         yield
         # TODO: also when dut.wr.go is set, check the output against the
-        # self.expected_o and assert
+        # self.expected_o and assert.  use dut.get_out(wr_idx) to do so.
 
 def test_compunit_regspec1():
     from alu_hier import ALU