From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 19 Jul 2019 21:40:57 +0000 (-0700)
Subject: Try and fix again
X-Git-Tag: working-ls180~1163^2~7
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=09beeee38a5af767f70d24e86c976e43b1b27547;p=yosys.git

Try and fix again
---

diff --git a/passes/opt/wreduce.cc b/passes/opt/wreduce.cc
index 908a85d5b..22af0bd8b 100644
--- a/passes/opt/wreduce.cc
+++ b/passes/opt/wreduce.cc
@@ -372,13 +372,12 @@ struct WreduceWorker
 
 			int i;
 			for (i = 0; i < GetSize(sig); i++) {
-				if (B.at(i, Sx) != S0 && (sub || A.at(i, Sx) != S0))
-					break;
-				if (B[i] == S0)
+				if (B.at(i, Sx) == S0 && A.at(i, Sx) != Sx)
 					module->connect(sig[i], A[i]);
-				else if (A[i] == S0)
+				else if (!sub && A.at(i, Sx) == S0 && B.at(i, Sx) != Sx)
 					module->connect(sig[i], B[i]);
-				else log_abort();
+				else
+					break;
 			}
 			if (i > 0) {
 				cell->setPort("\\A", A.extract(i, -1));