From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Tue, 30 Jul 2019 11:00:32 +0000 (+0100)
Subject: remove default and swap over DIV/SQRT operations, to make SQRT the default
X-Git-Tag: ls180-24jan2020~660
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=09c37ea65fc5c4102fb8f71152e0bda0a03c1a04;p=ieee754fpu.git

remove default and swap over DIV/SQRT operations, to make SQRT the default

http://bugs.libre-riscv.org/show_bug.cgi?id=126
---

diff --git a/src/ieee754/div_rem_sqrt_rsqrt/core.py b/src/ieee754/div_rem_sqrt_rsqrt/core.py
index 507caf28..cef62a34 100644
--- a/src/ieee754/div_rem_sqrt_rsqrt/core.py
+++ b/src/ieee754/div_rem_sqrt_rsqrt/core.py
@@ -59,8 +59,8 @@ class DivPipeCoreOperation(enum.Enum):
     :attribute RSqrtRem: reciprocal-square-root/remainder.
     """
 
-    UDivRem = 0
-    SqrtRem = 1
+    SqrtRem = 0
+    UDivRem = 1
     RSqrtRem = 2
 
     def __int__(self):
diff --git a/src/ieee754/fpdiv/div0.py b/src/ieee754/fpdiv/div0.py
index 7a39d727..4b9f25a9 100644
--- a/src/ieee754/fpdiv/div0.py
+++ b/src/ieee754/fpdiv/div0.py
@@ -88,9 +88,6 @@ class FPDivStage0Mod(Elaboratable):
                  self.o.divisor_radicand.eq(divr_rad),
         ]
 
-        # set default since it's not always set; non-zero value for debugging
-        comb += self.o.operation.eq(1)
-
         with m.If(~self.i.out_do_z):
             # DIV
             with m.If(self.i.ctx.op == int(DPCOp.UDivRem)):