From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 19 Nov 2019 23:40:39 +0000 (-0800)
Subject: Merge remote-tracking branch 'origin/master' into xaig_dff
X-Git-Tag: working-ls180~881^2^2~167
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=09ee96e8c22ec692ee3ee31b8c211646eabbcf27;p=yosys.git

Merge remote-tracking branch 'origin/master' into xaig_dff
---

09ee96e8c22ec692ee3ee31b8c211646eabbcf27
diff --cc techlibs/xilinx/synth_xilinx.cc
index a5358cf64,3d4a65c5d..b5c203d1f
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@@ -283,30 -291,12 +291,13 @@@ struct SynthXilinxPass : public ScriptP
  			ff_map_file = "+/xilinx/xc7_ff_map.v";
  
  		if (check_label("begin")) {
 +			std::string read_args;
  			if (vpr)
 -				run("read_verilog -lib -D_EXPLICIT_CARRY +/xilinx/cells_sim.v");
 -			else
 -				run("read_verilog -lib +/xilinx/cells_sim.v");
 +				read_args += " -D_EXPLICIT_CARRY";
 +			read_args += " -lib +/xilinx/cells_sim.v";
 +			run("read_verilog" + read_args);
  
- 			if (help_mode)
- 				run("read_verilog -lib +/xilinx/{family}_cells_xtra.v");
- 			else if (family == "xc6s")
- 				run("read_verilog -lib +/xilinx/xc6s_cells_xtra.v");
- 			else if (family == "xc6v")
- 				run("read_verilog -lib +/xilinx/xc6v_cells_xtra.v");
- 			else if (family == "xc7")
- 				run("read_verilog -lib +/xilinx/xc7_cells_xtra.v");
- 			else if (family == "xcu" || family == "xcup")
- 				run("read_verilog -lib +/xilinx/xcu_cells_xtra.v");
- 
- 			if (help_mode) {
- 				run("read_verilog -lib +/xilinx/{family}_brams_bb.v");
- 			} else if (family == "xc6s") {
- 				run("read_verilog -lib +/xilinx/xc6s_brams_bb.v");
- 			} else if (family == "xc6v" || family == "xc7") {
- 				run("read_verilog -lib +/xilinx/xc7_brams_bb.v");
- 			}
+ 			run("read_verilog -lib +/xilinx/cells_xtra.v");
  
  			run(stringf("hierarchy -check %s", top_opt.c_str()));
  		}