From: Clifford Wolf <clifford@clifford.at>
Date: Sat, 1 Jul 2017 14:05:26 +0000 (+0200)
Subject: Fix and_or_buffer optimization in opt_expr for signed operators
X-Git-Tag: yosys-0.8~408
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=0a02cdb93bfff64eb434e4cabbc9f007c4755647;p=yosys.git

Fix and_or_buffer optimization in opt_expr for signed operators
---

diff --git a/passes/opt/opt_expr.cc b/passes/opt/opt_expr.cc
index 07cdf4652..f9e40869d 100644
--- a/passes/opt/opt_expr.cc
+++ b/passes/opt/opt_expr.cc
@@ -371,13 +371,13 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
 		if (cell->type.in("$reduce_and", "$_AND_"))
 			detect_const_and = true;
 
-		if (cell->type.in("$and", "$logic_and") && GetSize(cell->getPort("\\A")) == 1 && GetSize(cell->getPort("\\B")) == 1)
+		if (cell->type.in("$and", "$logic_and") && GetSize(cell->getPort("\\A")) == 1 && GetSize(cell->getPort("\\B")) == 1 && !cell->getParam("\\A_SIGNED").as_bool())
 			detect_const_and = true;
 
 		if (cell->type.in("$reduce_or", "$reduce_bool", "$_OR_"))
 			detect_const_or = true;
 
-		if (cell->type.in("$or", "$logic_or") && GetSize(cell->getPort("\\A")) == 1 && GetSize(cell->getPort("\\B")) == 1)
+		if (cell->type.in("$or", "$logic_or") && GetSize(cell->getPort("\\A")) == 1 && GetSize(cell->getPort("\\B")) == 1 && !cell->getParam("\\A_SIGNED").as_bool())
 			detect_const_or = true;
 
 		if (detect_const_and || detect_const_or)