From: lkcl Date: Thu, 28 Apr 2022 17:08:45 +0000 (+0100) Subject: (no commit message) X-Git-Tag: opf_rfc_ls005_v1~2549 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=0a0a3e7f45fc34ccd5fc47e8786320dcbea22145;p=libreriscv.git --- diff --git a/openpower/sv/biginteger/analysis.mdwn b/openpower/sv/biginteger/analysis.mdwn index a435b12f4..c908420a8 100644 --- a/openpower/sv/biginteger/analysis.mdwn +++ b/openpower/sv/biginteger/analysis.mdwn @@ -284,7 +284,7 @@ detect*). SVP64 has the means to mark registers as scalar or vector. However the available space in the prefix is extremely limited (9 bits). With effectively 5 operands (3 in, 2 out) some compromises are needed. -A little though gives a useful workaround: two modes, +A little thought gives a useful workaround: two modes, controlled by a single bit in `RM.EXTRA`, determine whether the 5th register is set to RC or whether to RT+VL. This then leaves only 4 registers to qualify as scalar/vector, which can use four