From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Tue, 23 Jun 2020 15:47:54 +0000 (+0100)
Subject: TstL0CacheBuffer returns array of ports differently now
X-Git-Tag: div_pipeline~293
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=0a0aaa1a67dc51cb6de334353ddeba061945f37c;p=soc.git

TstL0CacheBuffer returns array of ports differently now
---

diff --git a/src/soc/simple/core.py b/src/soc/simple/core.py
index e52aac64..f19fe9f9 100644
--- a/src/soc/simple/core.py
+++ b/src/soc/simple/core.py
@@ -56,7 +56,7 @@ class NonProductionCore(Elaboratable):
     def __init__(self, addrwid=6, idepth=16):
         # single LD/ST funnel for memory access
         self.l0 = TstL0CacheBuffer(n_units=1, regwid=64, addrwid=addrwid)
-        pi = self.l0.l0.dports[0].pi
+        pi = self.l0.l0.dports[0]
 
         # function units (only one each)
         self.fus = AllFunctionUnits(pilist=[pi], addrwid=addrwid)