From: Eddie Hung <eddie@fpgeh.com>
Date: Mon, 30 Sep 2019 21:52:04 +0000 (-0700)
Subject: Fix for svinterfaces
X-Git-Tag: working-ls180~1019^2
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=0a1af434e8acfaa692d7990bce68fd23daed9519;p=yosys.git

Fix for svinterfaces
---

diff --git a/frontends/ast/ast.cc b/frontends/ast/ast.cc
index e4539f303..37a69d8bf 100644
--- a/frontends/ast/ast.cc
+++ b/frontends/ast/ast.cc
@@ -1398,11 +1398,17 @@ RTLIL::IdString AstModule::derive(RTLIL::Design *design, dict<RTLIL::IdString, R
 		has_interfaces = true;
 	}
 
+	std::string new_modname = modname;
 	if (has_interfaces)
-		modname += "$interfaces$" + interf_info;
+		new_modname += "$interfaces$" + interf_info;
 
 
-	if (!design->has(modname)) {
+	if (!design->has(new_modname)) {
+		if (!new_ast) {
+			auto mod = dynamic_cast<AstModule*>(design->module(modname));
+			new_ast = mod->ast->clone();
+		}
+		modname = new_modname;
 		new_ast->str = modname;
 
 		// Iterate over all interfaces which are ports in this module: