From: lkcl <lkcl@web>
Date: Sun, 4 Apr 2021 14:14:03 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: DRAFT_SVP64_0_1~1082
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=0a2a8e18631620805309ca00da8199d23fd25b59;p=libreriscv.git

---

diff --git a/openpower/sv/svp64/appendix.mdwn b/openpower/sv/svp64/appendix.mdwn
index fb2490c53..3e9955c47 100644
--- a/openpower/sv/svp64/appendix.mdwn
+++ b/openpower/sv/svp64/appendix.mdwn
@@ -113,6 +113,12 @@ retain their v3.0B / v3.1B OpenPOWER Standard compliant meaning.
     111 |        |       | EXT58 | EXT59 |       | EXT61  |       | EXT63 | 111
         |  000   |   001 |   010 |  011  |   100 |   101  | 110   |  111
 
+# Single Predication
+
+This is a standard mode normally found in Vector ISAs.  every element in rvery source Vector and in the destination uses the same bit of one single predicate mask.
+
+Note however that in SVSTATE, implementors MUST increment both srcstep and dststep, and that the two must be equal at all times.
+
 # Twin Predication
 
 This is a novel concept that allows predication to be applied to a single