From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Mon, 25 May 2020 13:43:15 +0000 (+0100)
Subject: add INT, SPR and CR regfiles
X-Git-Tag: div_pipeline~844
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=0a325453d3017b59bc7d4e5dfeb6a3c865a49e01;p=soc.git

add INT, SPR and CR regfiles
---

diff --git a/src/soc/decoder/power_enums.py b/src/soc/decoder/power_enums.py
index d8a78e99..05e23f8e 100644
--- a/src/soc/decoder/power_enums.py
+++ b/src/soc/decoder/power_enums.py
@@ -267,3 +267,11 @@ XER_bits = {
     'OV32': 44,
     'CA32': 45
     }
+
+if __name__ == '__main__':
+    # find out what the heck is in SPR enum :)
+    print ("sprs", len(SPR))
+    print (dir(SPR))
+    print (dir(Enum))
+    for x in SPR:
+        print (x, x.value)
diff --git a/src/soc/regfile/regfiles.py b/src/soc/regfile/regfiles.py
index b848ea47..d6f3a8dd 100644
--- a/src/soc/regfile/regfiles.py
+++ b/src/soc/regfile/regfiles.py
@@ -17,3 +17,56 @@ Links:
 """
 
 # TODO
+
+from soc.regfile import RegFile, RegFileArray
+from soc.decoder.power_enums import SPR
+
+
+# Integer Regfile
+class IntRegs(RegFileArray):
+    """IntRegs
+
+    * QTY 32of 64-bit registers
+    * 3R1W
+    * Array-based unary-indexed (not binary-indexed)
+    * write-through capability (read on same cycle as write)
+    """
+    def __init__(self):
+        super().__init__(64, 32)
+        self.w_ports = [self.write_port("dest")]
+        self.r_ports = [self.write_port("src1"),
+                        self.write_port("src2"),
+                        self.write_port("src3")]
+
+
+# CR Regfile
+class CRRegs(RegFileArray):
+    """Condition Code Registers (CR0-7)
+
+    * QTY 8of 8-bit registers
+    * 8R8W (!) with additional 1R1W for the "full" width
+    * Array-based unary-indexed (not binary-indexed)
+    * write-through capability (read on same cycle as write)
+    """
+    def __init__(self):
+        super().__init__(4, 8)
+        self.w_ports = [self.write_port("dest")]
+        self.r_ports = [self.write_port("src1"),
+                        self.write_port("src2"),
+                        self.write_port("src3")]
+
+
+# SPR Regfile
+class SPRRegs(RegFile):
+    """SPRRegs
+
+    * QTY len(SPRs) 64-bit registers
+    * 1R1W
+    * binary-indexed but REQUIRES MAPPING
+    * write-through capability (read on same cycle as write)
+    """
+    def __init__(self):
+        n_sprs = len(SPR)
+        super().__init__(64, n_sprs)
+        self.w_ports = [self.write_port("dest")]
+        self.r_ports = [self.write_port("src")]