From: lkcl <lkcl@web>
Date: Sun, 14 Nov 2021 18:21:53 +0000 (+0000)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~3388
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=0a3d1ab7d6d75771e7d8051650fa5b25a4ea6910;p=libreriscv.git

---

diff --git a/docs/pinmux.mdwn b/docs/pinmux.mdwn
index 4dfde8ba4..45b1a8d82 100644
--- a/docs/pinmux.mdwn
+++ b/docs/pinmux.mdwn
@@ -9,8 +9,9 @@ Links:
 
 Managing IO on an ASIC is nowhere near as simple as on an FPGA.
 An FPGA has built-in IO Pads, the wires terminate inside an
-existing silicon block which has been tested for you.  In an
-ASIC, a bi-directional IO Pad requires three wires (in, out,
+existing silicon block which has been tested for you.
+In an ASIC, you are going to have to do everything yourself.
+In an ASIC, a bi-directional IO Pad requires three wires (in, out,
 out-enable) to be routed right the way from the ASIC, all
 the way to the IO PAD, where only then does a wire bond connect
 it to a single pin.