From: Tobias Platen <tplaten@posteo.de>
Date: Tue, 12 Apr 2022 18:48:39 +0000 (+0200)
Subject: revert changes in wishbone_bram_wrapper.vhdl
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=0a47c560d87ed77858a95d4340e8435eef3ba47e;p=microwatt.git

revert changes in wishbone_bram_wrapper.vhdl
---

diff --git a/wishbone_bram_wrapper.vhdl b/wishbone_bram_wrapper.vhdl
index fcf528b..ced0431 100644
--- a/wishbone_bram_wrapper.vhdl
+++ b/wishbone_bram_wrapper.vhdl
@@ -76,7 +76,8 @@ begin
     bram_re <= ram_re;
 
     -- Wishbone interface
-    ram_addr <= wishbone_in.adr(ram_addr_bits + 2 downto 3);
+    ram_addr <= wishbone_in.adr(ram_addr_bits - 1 downto 0);
+    -- not that a wishbone compliant version of libre-soc is needed
     ram_we <= wishbone_in.stb and wishbone_in.cyc and wishbone_in.we;
     ram_re <= wishbone_in.stb and wishbone_in.cyc and not wishbone_in.we;
     wishbone_out.stall <= '0';