From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Wed, 5 Aug 2020 14:26:49 +0000 (+0000)
Subject: workaround for spr bug
X-Git-Tag: partial-core-ls180-gdsii~93
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=0a54b783281715f4e972052899ef779ea86e904f;p=soclayout.git

workaround for spr bug
https://gitlab.lip6.fr/vlsi-eda/coriolis/-/issues/23
reduce height of SPR block
---

diff --git a/experiments9/doDesign.py b/experiments9/doDesign.py
index 53602e7..bd0d61c 100644
--- a/experiments9/doDesign.py
+++ b/experiments9/doDesign.py
@@ -474,7 +474,7 @@ def scriptMain ( **kw ):
         blockSpr0.state.cfg.etesian.uniformDensity = True
         blockSpr0.state.cfg.etesian.spaceMargin    = 0.5
         blockSpr0.state.cfg.katana.searchHalo      = 1
-        blockSpr0.state.fixedHeight = l(5000)
+        blockSpr0.state.fixedHeight = l(4500)
         blockSpr0.state.useSpares   = False
        #rvalue = blockSpr0.build()