From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Thu, 4 Jun 2020 20:53:20 +0000 (+0100)
Subject: testing CRs after writing: not in the right bit-order
X-Git-Tag: div_pipeline~572
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=0a5d285bb5c557cd7fb3db9642372425562fca68;p=soc.git

testing CRs after writing: not in the right bit-order
---

diff --git a/src/soc/simple/test/test_core.py b/src/soc/simple/test/test_core.py
index 96abda8d..0cb97a59 100644
--- a/src/soc/simple/test/test_core.py
+++ b/src/soc/simple/test/test_core.py
@@ -147,6 +147,20 @@ class TestRunner(FHDLTestCase):
                         self.assertEqual(simregval, intregs[i],
                             "int reg %d not equal %s" % (i, repr(code)))
 
+                    # CRs
+                    crregs = []
+                    for i in range(8):
+                        rval = yield core.regs.cr.regs[i].reg
+                        crregs.append(rval)
+                    print ("cr regs", list(map(hex, crregs)))
+                    print ("sim cr reg", hex(cr))
+                    for i in range(8):
+                        rval = crregs[i]
+                        cri = sim.crl[7-i].get_range().value
+                        print ("cr reg", i, hex(cri), i, hex(rval))
+                        self.assertEqual(cri, rval,
+                            "cr reg %d not equal %s" % (i, repr(code)))
+
         sim.add_sync_process(process)
         with sim.write_vcd("core_simulator.vcd", "core_simulator.gtkw",
                             traces=[]):