From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 6 Jun 2019 21:01:42 +0000 (-0700)
Subject: Fix warnings
X-Git-Tag: yosys-0.9~48^2~23
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=0a66720f6f67b087fe6342d01d45944506240942;p=yosys.git

Fix warnings
---

diff --git a/tests/various/muxpack.v b/tests/various/muxpack.v
index fe0150532..7c189fff8 100644
--- a/tests/various/muxpack.v
+++ b/tests/various/muxpack.v
@@ -74,7 +74,7 @@ always @*
     else o <= {W{1'bx}};
 endmodule
 
-module mux_if_unbal_5_3_nonexcl #(parameter N=4, parameter W=1) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o);
+module mux_if_unbal_5_3_nonexcl #(parameter N=5, parameter W=3) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o);
 always @* begin
     o <= {W{1'bx}};
     if (s == 0) o <= i[0*W+:W];
@@ -86,7 +86,7 @@ always @* begin
 end
 endmodule
 
-module mux_case_unbal_7_7#(parameter N=7, parameter W=7) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o);
+module mux_case_unbal_8_7#(parameter N=8, parameter W=7) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o);
 always @* begin
     o <= {W{1'bx}};
     case (s)
diff --git a/tests/various/muxpack.ys b/tests/various/muxpack.ys
index 4dcb9ed89..0c5b82818 100644
--- a/tests/various/muxpack.ys
+++ b/tests/various/muxpack.ys
@@ -120,7 +120,7 @@ miter -equiv -flatten -make_assert -make_outputs gold gate miter
 sat -verify -prove-asserts -show-ports miter
 
 design -load read
-hierarchy -top mux_case_unbal_7_7
+hierarchy -top mux_case_unbal_8_7
 prep
 design -save gold
 muxpack