From: Sagar Ghuge Date: Sat, 20 Oct 2018 01:25:23 +0000 (-0700) Subject: intel/compiler: Change src1 reg type to unsigned doubleword X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=0a7664fe8c79580d3f1702ae1106c6824b3fbf2b;p=mesa.git intel/compiler: Change src1 reg type to unsigned doubleword To have uniform behavior while disassembling send(c) instruction use register type of unsigned doubleword for src1 when message descriptor is immediate value. Bspec does not specifiy anything for src1 immediate default type. Reviewed-by: Samuel Iglesias Gonsálvez Reviewed-by: Matt Turner Signed-off-by: Sagar Ghuge --- diff --git a/src/intel/compiler/brw_eu_emit.c b/src/intel/compiler/brw_eu_emit.c index 0cbc682ebcf..4630b83b1a0 100644 --- a/src/intel/compiler/brw_eu_emit.c +++ b/src/intel/compiler/brw_eu_emit.c @@ -371,7 +371,7 @@ brw_set_desc_ex(struct brw_codegen *p, brw_inst *inst, assert(brw_inst_opcode(devinfo, inst) == BRW_OPCODE_SEND || brw_inst_opcode(devinfo, inst) == BRW_OPCODE_SENDC); brw_inst_set_src1_file_type(devinfo, inst, - BRW_IMMEDIATE_VALUE, BRW_REGISTER_TYPE_D); + BRW_IMMEDIATE_VALUE, BRW_REGISTER_TYPE_UD); brw_inst_set_send_desc(devinfo, inst, desc); if (devinfo->gen >= 9) brw_inst_set_send_ex_desc(devinfo, inst, ex_desc); diff --git a/src/intel/compiler/brw_fs_generator.cpp b/src/intel/compiler/brw_fs_generator.cpp index cb402cd4e75..08dd83dded7 100644 --- a/src/intel/compiler/brw_fs_generator.cpp +++ b/src/intel/compiler/brw_fs_generator.cpp @@ -630,7 +630,7 @@ fs_generator::generate_urb_write(fs_inst *inst, struct brw_reg payload) brw_set_dest(p, insn, brw_null_reg()); brw_set_src0(p, insn, payload); - brw_set_src1(p, insn, brw_imm_d(0)); + brw_set_src1(p, insn, brw_imm_ud(0u)); brw_inst_set_sfid(p->devinfo, insn, BRW_SFID_URB); brw_inst_set_urb_opcode(p->devinfo, insn, GEN8_URB_OPCODE_SIMD8_WRITE); @@ -659,7 +659,7 @@ fs_generator::generate_cs_terminate(fs_inst *inst, struct brw_reg payload) brw_set_dest(p, insn, retype(brw_null_reg(), BRW_REGISTER_TYPE_UW)); brw_set_src0(p, insn, retype(payload, BRW_REGISTER_TYPE_UW)); - brw_set_src1(p, insn, brw_imm_d(0)); + brw_set_src1(p, insn, brw_imm_ud(0u)); /* Terminate a compute shader by sending a message to the thread spawner. */