From: lkcl <lkcl@web>
Date: Wed, 20 Apr 2022 19:27:31 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~2667
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=0a7ef71379a0fc083181215ba6581bf7b028032f;p=libreriscv.git

---

diff --git a/openpower/sv/biginteger.mdwn b/openpower/sv/biginteger.mdwn
index 9c083c570..3799f22d8 100644
--- a/openpower/sv/biginteger.mdwn
+++ b/openpower/sv/biginteger.mdwn
@@ -213,7 +213,7 @@ Note that RC is not sign-extended to 64-bit.  In a Vector Loop
 it contains the top half of the previous multiply-with-subtract,
 and the current product must be subtracted from it.
 
-The pseudocode for `maddx RT, RA, RB, RC` is:
+The pseudocode for `madded RT, RA, RB, RC` is:
 
     prod[0:127] = (RA) * (RB)
     sum[0:127] = EXTZ(RC) + prod
@@ -224,6 +224,10 @@ Again RC is zero-extended (not shifted), the 128-bit product added
 to it; the lower half of the result stored in RT and the upper half
 in RS.
 
+The differences here to `maddhdu` are that `maddhdu` stores the upper
+half in RT, where `madded` stores the upper half in RS. There is no
+equivalent to `maddld` because `maddld` performs sign-extension on RC.
+
 # Appendix
 
 see [[appendix]]