From: lkcl <lkcl@web>
Date: Sat, 7 May 2022 15:56:16 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~2321
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=0a873ae35b9633a01c0090a30d919cc8c979cdfc;p=libreriscv.git

---

diff --git a/openpower/sv/SimpleV_rationale.mdwn b/openpower/sv/SimpleV_rationale.mdwn
index 6a36c5765..17a783f01 100644
--- a/openpower/sv/SimpleV_rationale.mdwn
+++ b/openpower/sv/SimpleV_rationale.mdwn
@@ -167,6 +167,9 @@ candidates for further advancement are:
 * RISC-V, touted as "Open" but actually strictly controlled under
   Trademark License: too new to have adequate patent pool protection,
   as evidenced by multiple adopters having been hit by patent lawsuits.
+  (Agreements between RISC-V *Members* to not engage in patent litigation
+   does nothing to stop third party patents that *legitimately pre-date*
+   the newly-created RISC-V ISA)
 * MIPS, SPARC, ARC, and others, simply have no viable ecosystem.
 * Power ISA: protected by IBM's extensive patent portfolio for Members
   of the OpenPOWER Foundation, covered by Trademarks, permitting