From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sat, 21 Apr 2018 22:50:18 +0000 (+0100)
Subject: add duplication analysis
X-Git-Tag: convert-csv-opcode-to-binary~5610
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=0a9cd42f66c016bd175953cce0b07c3baa1329e2;p=libreriscv.git

add duplication analysis
---

diff --git a/simple_v_extension.mdwn b/simple_v_extension.mdwn
index 118dda9a9..61bd259dd 100644
--- a/simple_v_extension.mdwn
+++ b/simple_v_extension.mdwn
@@ -1595,3 +1595,4 @@ Also to be taken into consideration:
 * Discussion on RVV "re-entrant" capabilities allowing operations to be
   restarted if an exception occurs (VM page-table miss)
   <https://groups.google.com/a/groups.riscv.org/d/msg/isa-dev/IuNFitTw9fM/CCKBUlzsAAAJ>
+* Dot Product Vector <https://people.eecs.berkeley.edu/~biancolin/papers/arith17.pdf>
diff --git a/simple_v_extension/v_comparative_analysis.mdwn b/simple_v_extension/v_comparative_analysis.mdwn
index b2546275f..5a955d2e9 100644
--- a/simple_v_extension/v_comparative_analysis.mdwn
+++ b/simple_v_extension/v_comparative_analysis.mdwn
@@ -440,7 +440,7 @@ to produce the incremented address.  This does *not* require additional
 ports on the scalar register file, unlike scalar post-increment addressing
 modes.
 
-# TODO: instructions (based on Hwacha) V-Ext duplication analysis
+# TODO: instructions V-Ext duplication analysis <a name="duplication_analysis">
 
 This is partly speculative due to lack of access to an up-to-date
 V-Ext Spec (V2.3-draft RVV 0.4-Draft at the time of writing).  However