From: Nanley Chery <nanley.g.chery@intel.com>
Date: Wed, 21 Aug 2019 17:57:29 +0000 (-0700)
Subject: intel: Fix and use HIZ_CCS write through mode
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=0aa308f4200ad88c9b9ac0fd3e2ad30bde74edb9;p=mesa.git

intel: Fix and use HIZ_CCS write through mode

Write through to the CCS if the surface is used as a texture and can be
sampled by the HW with CCS.

Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
---

diff --git a/src/intel/genxml/gen12.xml b/src/intel/genxml/gen12.xml
index 8970ddf51a8..466ddb6894c 100644
--- a/src/intel/genxml/gen12.xml
+++ b/src/intel/genxml/gen12.xml
@@ -1893,6 +1893,7 @@
     <field name="Command SubType" start="27" end="28" type="uint" default="3"/>
     <field name="Command Type" start="29" end="31" type="uint" default="3"/>
     <field name="Surface Pitch" start="32" end="48" type="uint"/>
+    <field name="Hierarchical Depth Buffer Write Thru Enable" start="52" end="52" type="bool"/>
     <field name="Tiled Resource Mode" start="54" end="55" type="uint">
       <value name="NONE" value="0"/>
       <value name="TILEYF" value="1"/>
diff --git a/src/intel/isl/isl_emit_depth_stencil.c b/src/intel/isl/isl_emit_depth_stencil.c
index c3815a6ac56..fc2cf68ed4c 100644
--- a/src/intel/isl/isl_emit_depth_stencil.c
+++ b/src/intel/isl/isl_emit_depth_stencil.c
@@ -192,6 +192,12 @@ isl_genX(emit_depth_stencil_hiz_s)(const struct isl_device *dev, void *batch,
       hiz.SurfaceBaseAddress = info->hiz_address;
       hiz.MOCS = info->mocs;
       hiz.SurfacePitch = info->hiz_surf->row_pitch_B - 1;
+#if GEN_GEN >= 12
+      hiz.HierarchicalDepthBufferWriteThruEnable =
+         isl_surf_supports_hiz_ccs_wt(dev->info, info->depth_surf,
+                                      info->hiz_usage);
+#endif
+
 #if GEN_GEN >= 8
       /* From the SKL PRM Vol2a:
        *