From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Tue, 5 May 2020 14:33:14 +0000 (+0200)
Subject: targets/genesys2: set cmd_latency to 1.
X-Git-Tag: 24jan2021_ls180~382
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=0aa3c339ccfddad71657060448c72a3144879311;p=litex.git

targets/genesys2: set cmd_latency to 1.
---

diff --git a/litex/boards/targets/genesys2.py b/litex/boards/targets/genesys2.py
index 8557c0c5..d0b33def 100755
--- a/litex/boards/targets/genesys2.py
+++ b/litex/boards/targets/genesys2.py
@@ -56,7 +56,8 @@ class BaseSoC(SoCCore):
             self.submodules.ddrphy = s7ddrphy.K7DDRPHY(platform.request("ddram"),
                 memtype      = "DDR3",
                 nphases      = 4,
-                sys_clk_freq = sys_clk_freq)
+                sys_clk_freq = sys_clk_freq,
+                cmd_latency  = 1)
             self.add_csr("ddrphy")
             self.add_sdram("sdram",
                 phy                     = self.ddrphy,