From: Luke Kenneth Casson Leighton Date: Fri, 2 Oct 2020 10:03:18 +0000 (+0000) Subject: add really cut down version of ls180.vst X-Git-Tag: partial-core-ls180-gdsii~48 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=0aa7d759078648245d9f918932e6a446aa4a7530;p=soclayout.git add really cut down version of ls180.vst --- diff --git a/experiments9/non_generated/ls180.vst b/experiments9/non_generated/ls180.vst new file mode 100644 index 0000000..80d760e --- /dev/null +++ b/experiments9/non_generated/ls180.vst @@ -0,0 +1,95 @@ + +-- ======================================================================= +-- Coriolis Structural VHDL Driver +-- Generated on Oct 01, 2020, 15:11 +-- +-- Genarated with options: +-- * VstUseConcat: Use concat (&) in port map. +-- +-- To be interoperable with Alliance, it uses it's special VHDL subset. +-- ("man vhdl" under Alliance for more informations) +-- ======================================================================= + +entity ls180 is + port ( i2c_sda_i : in bit + ; jtag_tck : in bit + ; jtag_tdi : in bit + ; jtag_tms : in bit + ; sdcard_cmd_i : in bit + ; spi_master_miso : in bit + ; spisdcard_miso : in bit + ; sys_clk : in bit + ; sys_rst : in bit + ; uart_rx : in bit + ; eint : in bit_vector(2 downto 0) + ; sys_clksel_i : in bit_vector(2 downto 0) + ; sdcard_data_i : in bit_vector(3 downto 0) + ; gpio_i : in bit_vector(15 downto 0) + ; sdram_dq_i : in bit_vector(15 downto 0) + ; nc : in bit_vector(35 downto 0) + ; i2c_scl : out bit + ; i2c_sda_o : out bit + ; i2c_sda_oe : out bit + ; jtag_tdo : out bit + ; pwm0 : out bit + ; pwm1 : out bit + ; sdcard_clk : out bit + ; sdcard_cmd_o : out bit + ; sdcard_cmd_oe : out bit + ; sdcard_data_oe : out bit + ; sdram_cas_n : out bit + ; sdram_cke : out bit + ; sdram_clock : out bit + ; sdram_cs_n : out bit + ; sdram_dq_oe : out bit + ; sdram_ras_n : out bit + ; sdram_we_n : out bit + ; spi_master_clk : out bit + ; spi_master_cs_n : out bit + ; spi_master_mosi : out bit + ; spisdcard_clk : out bit + ; spisdcard_cs_n : out bit + ; spisdcard_mosi : out bit + ; sys_pll_48_o : out bit + ; uart_tx : out bit + ; sdram_ba : out bit_vector(1 downto 0) + ; sdram_dm : out bit_vector(1 downto 0) + ; sdcard_data_o : out bit_vector(3 downto 0) + ; sdram_a : out bit_vector(12 downto 0) + ; gpio_o : out bit_vector(15 downto 0) + ; gpio_oe : out bit_vector(15 downto 0) + ; sdram_dq_o : out bit_vector(15 downto 0) + ; vdd : linkage bit + ; vss : linkage bit + ); +end ls180; + +architecture structural of ls180 is + + component inv_x1 + port ( i : in bit + ; nq : out bit + ; vdd : in bit + ; vss : in bit + ); + end component; + + component zero_x0 + port ( nq : out bit + ; vdd : in bit + ; vss : in bit + ); + end component; + +begin + + zero_0 : zero_x0 + port map ( nq => pwm0 + , vdd => vdd + , vss => vss + ); + + + +end structural; +