From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 10 Jul 2019 23:23:15 +0000 (-0700)
Subject: Uncomment IS_C_INVERTED parameter
X-Git-Tag: working-ls180~881^2^2~280
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=0ab8f28bc7b6fefc1b4acd4e5c1cb437af878806;p=yosys.git

Uncomment IS_C_INVERTED parameter
---

diff --git a/techlibs/xilinx/abc_ff.v b/techlibs/xilinx/abc_ff.v
index 8bbdff6f4..d81f828e9 100644
--- a/techlibs/xilinx/abc_ff.v
+++ b/techlibs/xilinx/abc_ff.v
@@ -26,7 +26,7 @@ endmodule
 (* abc_box_id = 8, lib_whitebox, abc_flop = "FDRE,D,Q,\\$pastQ" *)
 module \$__ABC_FDRE (output Q, input C, CE, D, R, \$pastQ );
   parameter [0:0] INIT = 1'b0;
-  //parameter [0:0] IS_C_INVERTED = 1'b0;
+  parameter [0:0] IS_C_INVERTED = 1'b0;
   parameter [0:0] IS_D_INVERTED = 1'b0;
   parameter [0:0] IS_R_INVERTED = 1'b0;
   assign Q = (R ^ IS_R_INVERTED) ? 1'b0 : (CE ? (D ^ IS_D_INVERTED) : \$pastQ );