From: Aleksandar Kostovic <alexandar.kostovic@gmail.com>
Date: Thu, 14 Feb 2019 14:37:57 +0000 (+0100)
Subject: Translate put_z verilog case into nmigen
X-Git-Tag: ls180-24jan2020~1993
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=0afb5e8aee35febe485ae89eddea2292c79685a1;p=ieee754fpu.git

Translate put_z verilog case into nmigen
---

diff --git a/src/add/nmigen_add_experiment.py b/src/add/nmigen_add_experiment.py
index 24e87428..a69b77b2 100644
--- a/src/add/nmigen_add_experiment.py
+++ b/src/add/nmigen_add_experiment.py
@@ -330,17 +330,16 @@ class FPADD:
             # ******
             # put_z stage
 
-            """
-              put_z:
-              begin
-                s_out_z_stb <= 1;
-                s_out_z <= z;
-                if (s_out_z_stb && out_z_ack) begin
-                  s_out_z_stb <= 0;
-                  state <= get_a;
-                end
-              end
-            """
+            with m.State("put_z"):
+              m.next = "get_a"
+              m.d.sync += [
+                  s_out_z_stb.eq(1),
+                  s_out_z.eq(z)
+              ]
+              with m.If(s_out_z_stb & out_z_ack):
+                  m.d.sync += [
+                  s_out_z_stb.eq(0)
+                  ]
 
         return m