From: lkcl <lkcl@web>
Date: Sun, 16 Apr 2023 13:26:48 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls009_v1~6
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=0afcfaf0ba3daa36aa17a276c9d71fba3223468f;p=libreriscv.git

---

diff --git a/openpower/sv/normal.mdwn b/openpower/sv/normal.mdwn
index bc714a126..64a36687d 100644
--- a/openpower/sv/normal.mdwn
+++ b/openpower/sv/normal.mdwn
@@ -145,7 +145,8 @@ As explained in the [[sv/svp64/appendix]] Reduce Mode switches off the check
 which would normally stop looping if the result register is scalar.
 Thus, the result scalar register, if also used as a source scalar,
 may be used to perform sequential accumulation. This *deliberately*
-sets up a chain of Register Hazard Dependencies, whereas Parallel Reduce
+sets up a chain of Register Hazard Dependencies
+(which advanced hardware may optimise out), whereas Parallel Reduce
 [[sv/remap]] deliberately issues a Tree-Schedule of operations that may
 be parallelised.