From: Gabe Black <gblack@eecs.umich.edu>
Date: Wed, 2 Jun 2010 17:58:06 +0000 (-0500)
Subject: ARM: Decode the signed add/subtract and subtract/add instructions.
X-Git-Tag: stable_2012_02_02~1269
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=0aff168f1a3852150dc9520c294a60e8e5f917b9;p=gem5.git

ARM: Decode the signed add/subtract and subtract/add instructions.
---

diff --git a/src/arch/arm/isa/formats/data.isa b/src/arch/arm/isa/formats/data.isa
index 05d89abf5..cd902242e 100644
--- a/src/arch/arm/isa/formats/data.isa
+++ b/src/arch/arm/isa/formats/data.isa
@@ -236,9 +236,9 @@ def format ArmParallelAddSubtract() {{
                   case 0x0:
                     return new Sadd16RegCc(machInst, rd, rn, rm, 0, LSL);
                   case 0x1:
-                    return new WarnUnimplemented("sasx", machInst);
+                    return new SasxRegCc(machInst, rd, rn, rm, 0, LSL);
                   case 0x2:
-                    return new WarnUnimplemented("ssax", machInst);
+                    return new SsaxRegCc(machInst, rd, rn, rm, 0, LSL);
                   case 0x3:
                     return new Ssub16RegCc(machInst, rd, rn, rm, 0, LSL);
                   case 0x4:
@@ -553,9 +553,11 @@ def format Thumb32DataProcReg() {{
                             return new Sadd16RegCc(machInst, rd,
                                                    rn, rm, 0, LSL);
                           case 0x2:
-                            return new WarnUnimplemented("sasx", machInst);
+                            return new SasxRegCc(machInst, rd,
+                                                 rn, rm, 0, LSL);
                           case 0x6:
-                            return new WarnUnimplemented("ssax", machInst);
+                            return new SsaxRegCc(machInst, rd,
+                                                 rn, rm, 0, LSL);
                           case 0x5:
                             return new Ssub16RegCc(machInst, rd,
                                                    rn, rm, 0, LSL);