From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Mon, 24 Sep 2018 01:53:14 +0000 (+0100)
Subject: identify instructions, plan: extract registers
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=0b04753a1a57769a1d22b31883113b11815095f9;p=riscv-isa-sim.git

identify instructions, plan: extract registers
---

diff --git a/id_regs.py b/id_regs.py
new file mode 100644
index 0000000..c6c34ff
--- /dev/null
+++ b/id_regs.py
@@ -0,0 +1,30 @@
+#!/usr/bin/env python
+# Copyright (C) 2018 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+
+""" identify registers used in riscv/insns/*.h and create code
+    that can be used in spike at runtime
+
+    the design of spike assumes that once an opcode is identified,
+    the role of decoding the instruction is implicitly rolled into
+    and included inside the function that emulates that opcode.
+
+    however there may be circumstances where the behaviour of an
+    instruction has to change depending on "tags" associated with
+    the registers (security extensions, simple-v extension).
+"""
+
+import os
+
+def list_insns():
+    insns_dir = "./riscv/insns"
+    res = []
+    for fname in os.listdir(insns_dir):
+        if not fname.endswith(".h"):
+            continue
+        res.append(os.path.join(insns_dir, fname))
+    return res
+
+if __name__ == '__main__':
+    files = list_insns()
+    for f in files:
+        print f