From: Nathan Binkert <nate@binkert.org>
Date: Fri, 30 Jan 2009 06:27:11 +0000 (-0800)
Subject: Fix typo
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=0b228fc1ab7dbcf212a6d08aef8c7b7ff555a592;p=gem5.git

Fix typo
---

diff --git a/src/sim/System.py b/src/sim/System.py
index 5712a5c03..3b0bc1e46 100644
--- a/src/sim/System.py
+++ b/src/sim/System.py
@@ -38,7 +38,7 @@ class System(SimObject):
     type = 'System'
     swig_objdecls = [ '%include "python/swig/system.i"' ]
 
-    physmem = Param.PhysicalMemory(Parent.any, "phsyical memory")
+    physmem = Param.PhysicalMemory(Parent.any, "physical memory")
     mem_mode = Param.MemoryMode('atomic', "The mode the memory system is in")
     if build_env['FULL_SYSTEM']:
         abstract = True