From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Tue, 2 Jun 2020 20:36:11 +0000 (+0100)
Subject: add get_inputs function to branch test_pipe_caller
X-Git-Tag: div_pipeline~637^2~32
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=0b23589c7ba3a0a92fe5ebea67ef4822cb2990ba;p=soc.git

add get_inputs function to branch test_pipe_caller
---

diff --git a/src/soc/fu/branch/test/test_pipe_caller.py b/src/soc/fu/branch/test/test_pipe_caller.py
index b2b05f05..704cd7f9 100644
--- a/src/soc/fu/branch/test/test_pipe_caller.py
+++ b/src/soc/fu/branch/test/test_pipe_caller.py
@@ -219,6 +219,39 @@ class TestRunner(FHDLTestCase):
             branch_lr = yield branch.n.data_o.lr.data
             self.assertEqual(sim.spr['LR'], branch_lr, code)
 
+    def get_inputs(self, dec2, sim):
+        """naming (res) must conform to BranchFunctionUnit input regspec
+        """
+        res = {}
+
+        # CIA (PC)
+        res['cia'] = sim.pc.CIA.value
+
+        # CR A
+        cr1_en = yield dec2.e.read_cr1.ok
+        if cr1_en:
+            cr1_sel = yield dec2.e.read_cr1.data
+            res['cr_a'] = sim.crl[cr1_sel].get_range().value
+
+        # Fast1
+        spr_ok = yield dec2.e.read_fast1.ok
+        spr_num = yield dec2.e.read_fast1.data
+        # HACK
+        spr_num = fast_reg_to_spr(spr_num)
+        if spr_ok:
+            res['spr1'] = sim.spr[spr_dict[spr_num].SPR].value
+
+        # SPR2
+        spr_ok = yield dec2.e.read_fast2.ok
+        spr_num = yield dec2.e.read_fast2.data
+        # HACK
+        spr_num = fast_reg_to_spr(spr_num)
+        if spr_ok:
+            res['spr2'] = sim.spr[spr_dict[spr_num].SPR].value
+
+        print ("get inputs", res)
+        return res
+
     def set_inputs(self, branch, dec2, sim):
         yield branch.p.data_i.spr1.eq(sim.spr['CTR'].value)
         print(f"cr0: {sim.crl[0].get_range()}")