From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 5 Feb 2020 22:46:48 +0000 (-0800)
Subject: abc9_ops: -reintegrate to use derived_type for box_ports
X-Git-Tag: working-ls180~820
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=0b308c68357cc85876c3c86d6e5ac8b9318329ca;p=yosys.git

abc9_ops: -reintegrate to use derived_type for box_ports
---

diff --git a/passes/techmap/abc9_ops.cc b/passes/techmap/abc9_ops.cc
index 2b4a5c802..7071f0de4 100644
--- a/passes/techmap/abc9_ops.cc
+++ b/passes/techmap/abc9_ops.cc
@@ -797,7 +797,7 @@ void reintegrate(RTLIL::Module *module)
 			}
 
 			int input_count = 0, output_count = 0;
-			for (const auto &port_name : box_ports.at(cell->type)) {
+			for (const auto &port_name : box_ports.at(derived_type)) {
 				RTLIL::Wire *w = box_module->wire(port_name);
 				log_assert(w);
 
diff --git a/tests/arch/xilinx/dffs.ys b/tests/arch/xilinx/dffs.ys
index dc764b033..deaf16bd6 100644
--- a/tests/arch/xilinx/dffs.ys
+++ b/tests/arch/xilinx/dffs.ys
@@ -8,7 +8,6 @@ design -load postopt # load the post-opt design (otherwise equiv_opt loads the p
 cd dff # Constrain all select calls below inside the top module
 select -assert-count 1 t:BUFG
 select -assert-count 1 t:FDRE
-
 select -assert-none t:BUFG t:FDRE %% t:* %D
 
 
@@ -20,6 +19,27 @@ design -load postopt # load the post-opt design (otherwise equiv_opt loads the p
 cd dffe # Constrain all select calls below inside the top module
 select -assert-count 1 t:BUFG
 select -assert-count 1 t:FDRE
+select -assert-none t:BUFG t:FDRE %% t:* %D
+
+
+design -load read
+hierarchy -top dff
+proc
+equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -abc9 -dff -noiopad # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd dff # Constrain all select calls below inside the top module
+select -assert-count 1 t:BUFG
+select -assert-count 1 t:FDRE
+select -assert-none t:BUFG t:FDRE %% t:* %D
+
 
+design -load read
+hierarchy -top dffe
+proc
+equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -abc9 -dff -noiopad # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd dffe # Constrain all select calls below inside the top module
+select -assert-count 1 t:BUFG
+select -assert-count 1 t:FDRE
 select -assert-none t:BUFG t:FDRE %% t:* %D