From: Kenneth Graunke Date: Tue, 11 Dec 2018 08:34:11 +0000 (-0800) Subject: genxml: Consistently use a numeric "MOCS" field X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=0b44644ca6886de4201e3edd911b7d418a9d7680;p=mesa.git genxml: Consistently use a numeric "MOCS" field When we first started using genxml, we decided to represent MOCS as an actual structure, and pack values. However, in many places, it was more convenient to use a numeric value rather than treating it as a struct, so we added secondary setters in a bunch of places as well. We were not entirely consistent, either. Some places only had one. Gen6 had both kinds of setters for STATE_BASE_ADDRESS, but newer gens only had the struct-based setters. The names were sometimes "Constant Buffer Object Control State" instead of "Memory", making it harder to find. Many had prefixes like "Vertex Buffer MOCS"...in a vertex buffer packet...which is a bit redundant. On modern hardware, MOCS is simply an index into a table, but we were still carrying around the structure with an "Index to MOCS Table" field, in addition to the direct numeric setters. This is clunky - we really just want a number on new hardware. This patch eliminates the struct-based setters, and makes the numeric setters be consistently called "MOCS". We leave the struct definition around on Gen7-8 for reference purposes, but it is unused. v2: Drop bonus "Depth Buffer MOCS" fields on Gen7.5 and Gen9 Reviewed-by: Jordan Justen Reviewed-by: Kristian H. Kristensen --- diff --git a/src/intel/blorp/blorp_genX_exec.h b/src/intel/blorp/blorp_genX_exec.h index 065980616ec..42494ffbc86 100644 --- a/src/intel/blorp/blorp_genX_exec.h +++ b/src/intel/blorp/blorp_genX_exec.h @@ -311,7 +311,7 @@ blorp_fill_vertex_buffer_state(struct blorp_batch *batch, vb[idx].BufferPitch = stride; #if GEN_GEN >= 6 - vb[idx].VertexBufferMOCS = addr.mocs; + vb[idx].MOCS = addr.mocs; #endif #if GEN_GEN >= 7 diff --git a/src/intel/genxml/gen10.xml b/src/intel/genxml/gen10.xml index 2d3bc39b1b9..21cd8a17d91 100644 --- a/src/intel/genxml/gen10.xml +++ b/src/intel/genxml/gen10.xml @@ -219,14 +219,9 @@ - - - - - - + @@ -495,7 +490,6 @@ - @@ -993,7 +987,7 @@ - + @@ -1085,7 +1079,7 @@ - + @@ -1095,7 +1089,7 @@ - + @@ -1105,7 +1099,7 @@ - + @@ -1116,7 +1110,7 @@ - + @@ -1126,7 +1120,7 @@ - + @@ -1157,8 +1151,7 @@ - - + @@ -1368,7 +1361,7 @@ - + @@ -1447,8 +1440,7 @@ - - + @@ -1511,8 +1503,7 @@ - - + @@ -2068,8 +2059,7 @@ - - + @@ -2104,8 +2094,7 @@ - - + @@ -3318,20 +3307,20 @@ - + - + - + - + - + - + @@ -3342,11 +3331,11 @@ - + - + diff --git a/src/intel/genxml/gen11.xml b/src/intel/genxml/gen11.xml index 1239ed011ed..54816458fc3 100644 --- a/src/intel/genxml/gen11.xml +++ b/src/intel/genxml/gen11.xml @@ -220,14 +220,9 @@ - - - - - - + @@ -496,7 +491,6 @@ - @@ -1012,7 +1006,7 @@ - + @@ -1104,7 +1098,7 @@ - + @@ -1114,7 +1108,7 @@ - + @@ -1124,7 +1118,7 @@ - + @@ -1135,7 +1129,7 @@ - + @@ -1145,7 +1139,7 @@ - + @@ -1176,8 +1170,7 @@ - - + @@ -1386,7 +1379,7 @@ - + @@ -1463,8 +1456,7 @@ - - + @@ -1531,8 +1523,7 @@ - - + @@ -2088,8 +2079,7 @@ - - + @@ -2124,8 +2114,7 @@ - - + @@ -3321,20 +3310,20 @@ - + - + - + - + - + - + @@ -3345,11 +3334,11 @@ - + - + diff --git a/src/intel/genxml/gen6.xml b/src/intel/genxml/gen6.xml index fff1e5a8411..b4976b33c34 100644 --- a/src/intel/genxml/gen6.xml +++ b/src/intel/genxml/gen6.xml @@ -126,8 +126,7 @@ - - + @@ -384,7 +383,6 @@ - @@ -642,7 +640,7 @@ - + @@ -656,7 +654,7 @@ - + @@ -670,7 +668,7 @@ - + @@ -720,8 +718,7 @@ - - + @@ -804,8 +801,7 @@ - - + @@ -815,8 +811,7 @@ - - + @@ -1068,8 +1063,7 @@ - - + @@ -1696,26 +1690,20 @@ - - - - - - diff --git a/src/intel/genxml/gen7.xml b/src/intel/genxml/gen7.xml index 49b08281993..893c12b8af9 100644 --- a/src/intel/genxml/gen7.xml +++ b/src/intel/genxml/gen7.xml @@ -157,7 +157,7 @@ - + @@ -169,8 +169,7 @@ - - + @@ -443,7 +442,6 @@ - @@ -815,8 +813,7 @@ - - + @@ -949,8 +946,7 @@ - - + @@ -996,8 +992,7 @@ - - + @@ -1422,8 +1417,7 @@ - - + @@ -1454,8 +1448,7 @@ - - + @@ -2238,21 +2231,21 @@ - - + + - + - + - + - + @@ -2290,7 +2283,7 @@ - + diff --git a/src/intel/genxml/gen75.xml b/src/intel/genxml/gen75.xml index 6ce31b49241..009a123ad69 100644 --- a/src/intel/genxml/gen75.xml +++ b/src/intel/genxml/gen75.xml @@ -165,7 +165,7 @@ - + @@ -188,8 +188,7 @@ - - + @@ -463,7 +462,6 @@ - @@ -826,7 +824,7 @@ - + @@ -999,8 +997,7 @@ - - + @@ -1160,7 +1157,7 @@ - + @@ -1233,8 +1230,7 @@ - - + @@ -1284,8 +1280,7 @@ - - + @@ -1736,8 +1731,7 @@ - - + @@ -1769,8 +1763,7 @@ - - + @@ -2702,20 +2695,20 @@ - - + + - + - + - + - + @@ -2753,7 +2746,7 @@ - + diff --git a/src/intel/genxml/gen8.xml b/src/intel/genxml/gen8.xml index a27cac12843..fd19b0c8b33 100644 --- a/src/intel/genxml/gen8.xml +++ b/src/intel/genxml/gen8.xml @@ -216,8 +216,7 @@ - - + @@ -462,7 +461,6 @@ - @@ -894,7 +892,7 @@ - + @@ -986,7 +984,7 @@ - + @@ -996,7 +994,7 @@ - + @@ -1006,7 +1004,7 @@ - + @@ -1016,7 +1014,7 @@ - + @@ -1026,7 +1024,7 @@ - + @@ -1059,8 +1057,7 @@ - - + @@ -1221,7 +1218,7 @@ - + @@ -1299,8 +1296,7 @@ - - + @@ -1356,8 +1352,7 @@ - - + @@ -1837,8 +1832,7 @@ - - + @@ -1873,8 +1867,7 @@ - - + @@ -2962,20 +2955,20 @@ - + - + - + - + - + - + @@ -3013,7 +3006,7 @@ - + diff --git a/src/intel/genxml/gen9.xml b/src/intel/genxml/gen9.xml index 0f9a1d110e8..c8b090ac191 100644 --- a/src/intel/genxml/gen9.xml +++ b/src/intel/genxml/gen9.xml @@ -219,14 +219,9 @@ - - - - - - + @@ -494,7 +489,6 @@ - @@ -952,7 +946,7 @@ - + @@ -1044,7 +1038,7 @@ - + @@ -1054,7 +1048,7 @@ - + @@ -1064,7 +1058,7 @@ - + @@ -1074,7 +1068,7 @@ - + @@ -1084,7 +1078,7 @@ - + @@ -1115,8 +1109,7 @@ - - + @@ -1326,7 +1319,7 @@ - + @@ -1405,8 +1398,7 @@ - - + @@ -1469,8 +1461,7 @@ - - + @@ -2020,8 +2011,7 @@ - - + @@ -2056,8 +2046,7 @@ - - + @@ -3251,20 +3240,20 @@ - + - + - + - + - + - + @@ -3275,7 +3264,7 @@ - + diff --git a/src/intel/isl/isl_emit_depth_stencil.c b/src/intel/isl/isl_emit_depth_stencil.c index 9cf5a476687..d2dec3761e5 100644 --- a/src/intel/isl/isl_emit_depth_stencil.c +++ b/src/intel/isl/isl_emit_depth_stencil.c @@ -94,7 +94,7 @@ isl_genX(emit_depth_stencil_hiz_s)(const struct isl_device *dev, void *batch, #endif db.SurfaceBaseAddress = info->depth_address; #if GEN_GEN >= 6 - db.DepthBufferMOCS = info->mocs; + db.MOCS = info->mocs; #endif #if GEN_GEN <= 6 @@ -138,7 +138,7 @@ isl_genX(emit_depth_stencil_hiz_s)(const struct isl_device *dev, void *batch, #endif sb.SurfaceBaseAddress = info->stencil_address; #if GEN_GEN >= 6 - sb.StencilBufferMOCS = info->mocs; + sb.MOCS = info->mocs; #endif sb.SurfacePitch = info->stencil_surf->row_pitch_B - 1; #if GEN_GEN >= 8 @@ -161,7 +161,7 @@ isl_genX(emit_depth_stencil_hiz_s)(const struct isl_device *dev, void *batch, db.HierarchicalDepthBufferEnable = true; hiz.SurfaceBaseAddress = info->hiz_address; - hiz.HierarchicalDepthBufferMOCS = info->mocs; + hiz.MOCS = info->mocs; hiz.SurfacePitch = info->hiz_surf->row_pitch_B - 1; #if GEN_GEN >= 8 /* From the SKL PRM Vol2a: diff --git a/src/intel/vulkan/anv_private.h b/src/intel/vulkan/anv_private.h index aff076a55d9..b3e9ace7ad8 100644 --- a/src/intel/vulkan/anv_private.h +++ b/src/intel/vulkan/anv_private.h @@ -1349,64 +1349,50 @@ _anv_combine_address(struct anv_batch *batch, void *location, _dst = NULL; \ })) -#define GEN7_MOCS (struct GEN7_MEMORY_OBJECT_CONTROL_STATE) { \ - .GraphicsDataTypeGFDT = 0, \ - .LLCCacheabilityControlLLCCC = 0, \ - .L3CacheabilityControlL3CC = 1, \ -} +/* MEMORY_OBJECT_CONTROL_STATE: + * .GraphicsDataTypeGFDT = 0, + * .LLCCacheabilityControlLLCCC = 0, + * .L3CacheabilityControlL3CC = 1, + */ +#define GEN7_MOCS 1 -#define GEN75_MOCS (struct GEN75_MEMORY_OBJECT_CONTROL_STATE) { \ - .LLCeLLCCacheabilityControlLLCCC = 0, \ - .L3CacheabilityControlL3CC = 1, \ -} +/* MEMORY_OBJECT_CONTROL_STATE: + * .LLCeLLCCacheabilityControlLLCCC = 0, + * .L3CacheabilityControlL3CC = 1, + */ +#define GEN75_MOCS 1 -#define GEN8_MOCS (struct GEN8_MEMORY_OBJECT_CONTROL_STATE) { \ - .MemoryTypeLLCeLLCCacheabilityControl = WB, \ - .TargetCache = L3DefertoPATforLLCeLLCselection, \ - .AgeforQUADLRU = 0 \ - } +/* MEMORY_OBJECT_CONTROL_STATE: + * .MemoryTypeLLCeLLCCacheabilityControl = WB, + * .TargetCache = L3DefertoPATforLLCeLLCselection, + * .AgeforQUADLRU = 0 + */ +#define GEN8_MOCS 0x78 -#define GEN8_EXTERNAL_MOCS (struct GEN8_MEMORY_OBJECT_CONTROL_STATE) { \ - .MemoryTypeLLCeLLCCacheabilityControl = UCwithFenceifcoherentcycle, \ - .TargetCache = L3DefertoPATforLLCeLLCselection, \ - .AgeforQUADLRU = 0 \ - } +/* MEMORY_OBJECT_CONTROL_STATE: + * .MemoryTypeLLCeLLCCacheabilityControl = UCwithFenceifcoherentcycle, + * .TargetCache = L3DefertoPATforLLCeLLCselection, + * .AgeforQUADLRU = 0 + */ +#define GEN8_EXTERNAL_MOCS 0x18 /* Skylake: MOCS is now an index into an array of 62 different caching * configurations programmed by the kernel. */ -#define GEN9_MOCS (struct GEN9_MEMORY_OBJECT_CONTROL_STATE) { \ - /* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */ \ - .IndextoMOCSTables = 2 \ - } +/* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */ +#define GEN9_MOCS 2 -#define GEN9_EXTERNAL_MOCS (struct GEN9_MEMORY_OBJECT_CONTROL_STATE) { \ - /* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */ \ - .IndextoMOCSTables = 1 \ - } +/* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */ +#define GEN9_EXTERNAL_MOCS 1 /* Cannonlake MOCS defines are duplicates of Skylake MOCS defines. */ -#define GEN10_MOCS (struct GEN10_MEMORY_OBJECT_CONTROL_STATE) { \ - /* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */ \ - .IndextoMOCSTables = 2 \ - } - -#define GEN10_EXTERNAL_MOCS (struct GEN10_MEMORY_OBJECT_CONTROL_STATE) { \ - /* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */ \ - .IndextoMOCSTables = 1 \ - } +#define GEN10_MOCS GEN9_MOCS +#define GEN10_EXTERNAL_MOCS GEN9_EXTERNAL_MOCS /* Ice Lake MOCS defines are duplicates of Skylake MOCS defines. */ -#define GEN11_MOCS (struct GEN11_MEMORY_OBJECT_CONTROL_STATE) { \ - /* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */ \ - .IndextoMOCSTables = 2 \ - } - -#define GEN11_EXTERNAL_MOCS (struct GEN11_MEMORY_OBJECT_CONTROL_STATE) { \ - /* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */ \ - .IndextoMOCSTables = 1 \ - } +#define GEN11_MOCS GEN9_MOCS +#define GEN11_EXTERNAL_MOCS GEN9_EXTERNAL_MOCS struct anv_device_memory { struct anv_bo * bo; diff --git a/src/intel/vulkan/gen7_cmd_buffer.c b/src/intel/vulkan/gen7_cmd_buffer.c index da51cb9781c..08bebd44adb 100644 --- a/src/intel/vulkan/gen7_cmd_buffer.c +++ b/src/intel/vulkan/gen7_cmd_buffer.c @@ -246,7 +246,7 @@ genX(cmd_buffer_flush_dynamic_state)(struct anv_cmd_buffer *cmd_buffer) ib.CutIndexEnable = pipeline->primitive_restart; #endif ib.IndexFormat = cmd_buffer->state.gfx.gen7.index_type; - ib.IndexBufferMOCS = anv_mocs_for_bo(cmd_buffer->device, + ib.MOCS = anv_mocs_for_bo(cmd_buffer->device, buffer->address.bo); ib.BufferStartingAddress = anv_address_add(buffer->address, diff --git a/src/intel/vulkan/gen8_cmd_buffer.c b/src/intel/vulkan/gen8_cmd_buffer.c index 752d04f3013..5bacfed71c8 100644 --- a/src/intel/vulkan/gen8_cmd_buffer.c +++ b/src/intel/vulkan/gen8_cmd_buffer.c @@ -565,7 +565,7 @@ void genX(CmdBindIndexBuffer)( anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_INDEX_BUFFER), ib) { ib.IndexFormat = vk_to_gen_index_type[indexType]; - ib.IndexBufferMOCS = anv_mocs_for_bo(cmd_buffer->device, + ib.MOCS = anv_mocs_for_bo(cmd_buffer->device, buffer->address.bo); ib.BufferStartingAddress = anv_address_add(buffer->address, offset); ib.BufferSize = buffer->size - offset; diff --git a/src/intel/vulkan/genX_cmd_buffer.c b/src/intel/vulkan/genX_cmd_buffer.c index fb70cd2e386..1aaf83e97e8 100644 --- a/src/intel/vulkan/genX_cmd_buffer.c +++ b/src/intel/vulkan/genX_cmd_buffer.c @@ -86,26 +86,26 @@ genX(cmd_buffer_emit_state_base_address)(struct anv_cmd_buffer *cmd_buffer) anv_batch_emit(&cmd_buffer->batch, GENX(STATE_BASE_ADDRESS), sba) { sba.GeneralStateBaseAddress = (struct anv_address) { NULL, 0 }; - sba.GeneralStateMemoryObjectControlState = GENX(MOCS); + sba.GeneralStateMOCS = GENX(MOCS); sba.GeneralStateBaseAddressModifyEnable = true; sba.SurfaceStateBaseAddress = anv_cmd_buffer_surface_base_address(cmd_buffer); - sba.SurfaceStateMemoryObjectControlState = GENX(MOCS); + sba.SurfaceStateMOCS = GENX(MOCS); sba.SurfaceStateBaseAddressModifyEnable = true; sba.DynamicStateBaseAddress = (struct anv_address) { &device->dynamic_state_pool.block_pool.bo, 0 }; - sba.DynamicStateMemoryObjectControlState = GENX(MOCS); + sba.DynamicStateMOCS = GENX(MOCS); sba.DynamicStateBaseAddressModifyEnable = true; sba.IndirectObjectBaseAddress = (struct anv_address) { NULL, 0 }; - sba.IndirectObjectMemoryObjectControlState = GENX(MOCS); + sba.IndirectObjectMOCS = GENX(MOCS); sba.IndirectObjectBaseAddressModifyEnable = true; sba.InstructionBaseAddress = (struct anv_address) { &device->instruction_state_pool.block_pool.bo, 0 }; - sba.InstructionMemoryObjectControlState = GENX(MOCS); + sba.InstructionMOCS = GENX(MOCS); sba.InstructionBaseAddressModifyEnable = true; # if (GEN_GEN >= 8) @@ -124,13 +124,13 @@ genX(cmd_buffer_emit_state_base_address)(struct anv_cmd_buffer *cmd_buffer) # endif # if (GEN_GEN >= 9) sba.BindlessSurfaceStateBaseAddress = (struct anv_address) { NULL, 0 }; - sba.BindlessSurfaceStateMemoryObjectControlState = GENX(MOCS); + sba.BindlessSurfaceStateMOCS = GENX(MOCS); sba.BindlessSurfaceStateBaseAddressModifyEnable = true; sba.BindlessSurfaceStateSize = 0; # endif # if (GEN_GEN >= 10) sba.BindlessSamplerStateBaseAddress = (struct anv_address) { NULL, 0 }; - sba.BindlessSamplerStateMemoryObjectControlState = GENX(MOCS); + sba.BindlessSamplerStateMOCS = GENX(MOCS); sba.BindlessSamplerStateBaseAddressModifyEnable = true; sba.BindlessSamplerStateBufferSize = 0; # endif @@ -2572,8 +2572,7 @@ genX(cmd_buffer_flush_state)(struct anv_cmd_buffer *cmd_buffer) struct GENX(VERTEX_BUFFER_STATE) state = { .VertexBufferIndex = vb, - .VertexBufferMOCS = anv_mocs_for_bo(cmd_buffer->device, - buffer->address.bo), + .MOCS = anv_mocs_for_bo(cmd_buffer->device, buffer->address.bo), #if GEN_GEN <= 7 .BufferAccessType = pipeline->vb[vb].instanced ? INSTANCEDATA : VERTEXDATA, .InstanceDataStepRate = pipeline->vb[vb].instance_divisor, @@ -2691,7 +2690,7 @@ emit_vertex_bo(struct anv_cmd_buffer *cmd_buffer, .VertexBufferIndex = index, .AddressModifyEnable = true, .BufferPitch = 0, - .VertexBufferMOCS = anv_mocs_for_bo(cmd_buffer->device, addr.bo), + .MOCS = anv_mocs_for_bo(cmd_buffer->device, addr.bo), #if (GEN_GEN >= 8) .BufferStartingAddress = addr, .BufferSize = size diff --git a/src/intel/vulkan/genX_gpu_memcpy.c b/src/intel/vulkan/genX_gpu_memcpy.c index 1bee1c6dc17..ea35daa4126 100644 --- a/src/intel/vulkan/genX_gpu_memcpy.c +++ b/src/intel/vulkan/genX_gpu_memcpy.c @@ -167,7 +167,7 @@ genX(cmd_buffer_so_memcpy)(struct anv_cmd_buffer *cmd_buffer, .AddressModifyEnable = true, .BufferStartingAddress = src, .BufferPitch = bs, - .VertexBufferMOCS = anv_mocs_for_bo(cmd_buffer->device, src.bo), + .MOCS = anv_mocs_for_bo(cmd_buffer->device, src.bo), #if (GEN_GEN >= 8) .BufferSize = size, #else @@ -227,7 +227,7 @@ genX(cmd_buffer_so_memcpy)(struct anv_cmd_buffer *cmd_buffer, anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_SO_BUFFER), sob) { sob.SOBufferIndex = 0; - sob.SOBufferMOCS = anv_mocs_for_bo(cmd_buffer->device, dst.bo), + sob.MOCS = anv_mocs_for_bo(cmd_buffer->device, dst.bo), sob.SurfaceBaseAddress = dst; #if GEN_GEN >= 8 diff --git a/src/intel/vulkan/genX_state.c b/src/intel/vulkan/genX_state.c index 42800a2581e..0f6b77492fb 100644 --- a/src/intel/vulkan/genX_state.c +++ b/src/intel/vulkan/genX_state.c @@ -91,11 +91,9 @@ gen10_emit_wa_lri_to_cache_mode_zero(struct anv_batch *batch) VkResult genX(init_device_state)(struct anv_device *device) { - GENX(MEMORY_OBJECT_CONTROL_STATE_pack)(NULL, &device->default_mocs, - &GENX(MOCS)); + device->default_mocs = GENX(MOCS); #if GEN_GEN >= 8 - GENX(MEMORY_OBJECT_CONTROL_STATE_pack)(NULL, &device->external_mocs, - &GENX(EXTERNAL_MOCS)); + device->external_mocs = GENX(EXTERNAL_MOCS); #else device->external_mocs = device->default_mocs; #endif diff --git a/src/mesa/drivers/dri/i965/genX_state_upload.c b/src/mesa/drivers/dri/i965/genX_state_upload.c index bad0aff9c67..8c38d5f4e82 100644 --- a/src/mesa/drivers/dri/i965/genX_state_upload.c +++ b/src/mesa/drivers/dri/i965/genX_state_upload.c @@ -394,15 +394,15 @@ genX(emit_vertex_buffer_state)(struct brw_context *brw, #endif #if GEN_GEN == 11 - .VertexBufferMOCS = ICL_MOCS_WB, + .MOCS = ICL_MOCS_WB, #elif GEN_GEN == 10 - .VertexBufferMOCS = CNL_MOCS_WB, + .MOCS = CNL_MOCS_WB, #elif GEN_GEN == 9 - .VertexBufferMOCS = SKL_MOCS_WB, + .MOCS = SKL_MOCS_WB, #elif GEN_GEN == 8 - .VertexBufferMOCS = BDW_MOCS_WB, + .MOCS = BDW_MOCS_WB, #elif GEN_GEN == 7 - .VertexBufferMOCS = GEN7_MOCS_L3, + .MOCS = GEN7_MOCS_L3, #endif }; @@ -996,7 +996,7 @@ genX(emit_index_buffer)(struct brw_context *brw) */ ib.BufferStartingAddress = ro_32_bo(brw->ib.bo, 0); #if GEN_GEN >= 8 - ib.IndexBufferMOCS = GEN_GEN >= 9 ? SKL_MOCS_WB : BDW_MOCS_WB; + ib.MOCS = GEN_GEN >= 9 ? SKL_MOCS_WB : BDW_MOCS_WB; ib.BufferSize = brw->ib.size; #else ib.BufferEndingAddress = ro_bo(brw->ib.bo, brw->ib.size - 1); @@ -3878,7 +3878,7 @@ genX(upload_3dstate_so_buffers)(struct brw_context *brw) sob.SOBufferEnable = true; sob.StreamOffsetWriteEnable = true; sob.StreamOutputBufferOffsetAddressEnable = true; - sob.SOBufferMOCS = mocs_wb; + sob.MOCS = mocs_wb; sob.SurfaceSize = MAX2(xfb_obj->Size[i] / 4, 1) - 1; sob.StreamOutputBufferOffsetAddress =